H8/3068F Ver la hoja de datos (PDF) - Renesas Electronics

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H8/3068F

16-Bit Single-Chip Microcomputer

Renesas Electronics 

Section 5 Interrupt Controller .......................................................................................... 85

5.1 Overview........................................................................................................................... 85

5.1.1 Features................................................................................................................ 85

5.1.2 Block Diagram..................................................................................................... 86

5.1.3 Pin Configuration................................................................................................. 87

5.1.4 Register Configuration......................................................................................... 87

5.2 Register Descriptions........................................................................................................ 88

5.2.1 System Control Register (SYSCR) ...................................................................... 88

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 89

5.2.3 IRQ Status Register (ISR).................................................................................... 96

5.2.4 IRQ Enable Register (IER) .................................................................................. 97

5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 98

5.3 Interrupt Sources............................................................................................................... 99

5.3.1 External Interrupts ............................................................................................... 99

5.3.2 Internal Interrupts ................................................................................................ 100

5.3.3 Interrupt Vector Table ......................................................................................... 100

5.4 Interrupt Operation ........................................................................................................... 104

5.4.1 Interrupt Handling Process .................................................................................. 104

5.4.2 Interrupt Sequence ............................................................................................... 109

5.4.3 Interrupt Response Time...................................................................................... 110

5.5 Usage Notes ...................................................................................................................... 111

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 111

5.5.2 Instructions that Inhibit Interrupts ....................................................................... 112

5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 112

Section 6 Bus Controller ................................................................................................... 113

6.1 Overview........................................................................................................................... 113

6.1.1 Features................................................................................................................ 113

6.1.2 Block Diagram..................................................................................................... 115

6.1.3 Pin Configuration................................................................................................. 116

6.1.4 Register Configuration......................................................................................... 117

6.2 Register Descriptions........................................................................................................ 118

6.2.1 Bus Width Control Register (ABWCR)............................................................... 118

6.2.2 Access State Control Register (ASTCR) ............................................................. 119

6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 120

6.2.4 Bus Release Control Register (BRCR) ................................................................ 124

6.2.5 Bus Control Register (BCR) ................................................................................ 126

6.2.6 Chip Select Control Register (CSCR).................................................................. 129

6.2.7 DRAM Control Register A (DRCRA)................................................................. 130

6.2.8 DRAM Control Register B (DRCRB) ................................................................. 132

Rev. 3.00 Sep 14, 2005 page ix of xxii

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