H8/3004 Ver la hoja de datos (PDF) - Renesas Electronics

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H8/3004

Microcomputer

Renesas Electronics 

Table 1-1 Features

Feature

CPU

Memory

Interrupt

controller

Bus controller

16-bit integrated

timer unit (ITU)

Description

Upward-compatible with the H8/300 CPU at the object-code level

General-register machine

• Sixteen 16-bit general registers

(also useable as sixteen 8-bit registers or eight 32-bit registers)

High-speed operation

• Maximum clock rate: 16 MHz

• Add/subtract: 125 ns

• Multiply/divide: 875 ns

Two CPU operating modes

• Normal mode (64-kbyte address space; cannot be used with the H8/3004 or

H8/3005)

• Advanced mode (16-Mbyte address space)

Instruction features

• 8/16/32-bit data transfer, arithmetic, and logic instructions

• Signed and unsigned multiply instructions (8 bits ×8 bits, 16 bits ×16 bits)

• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)

• Bit accumulator function

• Bit manipulation instructions with register-indirect specification of bit positions

• H8/3004 RAM: 2 kbyte, H8/3005 RAM: 4 kbyte

• Six external interrupt pins: NMI, IRQ0 to IRQ4

• 21 internal interrupts

• Three selectable interrupt priority levels

• Address space can be partitioned into eight areas, with independent bus

specifications in each area

• Two-state or three-state access selectable for each area

• Selection of four wait modes

• Bus arbitration function

• Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10

pulse inputs

• 16-bit timer counter (channels 0 to 4)

• Two multiplexed output compare/input capture pins (channels 0 to 4)

• Operation can be synchronized (channels 0 to 4)

• PWM mode available (channels 0 to 4)

• Phase counting mode available (channel 2)

• Buffering available (channels 3 and 4)

• Reset-synchronized PWM mode available (channels 3 and 4)

• Complementary PWM mode available (channels 3 and 4)

2

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