H8/3004 Ver la hoja de datos (PDF) - Renesas Electronics
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H8/3004 Datasheet PDF : 497 Pages
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10.2 Register Descriptions...................................................................................................... 265
10.2.1 Receive Shift Register (RSR) ......................................................................... 265
10.2.2 Receive Data Register (RDR)......................................................................... 265
10.2.3 Transmit Shift Register (TSR) ........................................................................ 266
10.2.4 Transmit Data Register (TDR)........................................................................ 266
10.2.5 Serial Mode Register (SMR) .......................................................................... 267
10.2.6 Serial Control Register (SCR) ........................................................................ 271
10.2.7 Serial Status Register (SSR) ........................................................................... 275
10.2.8 Bit Rate Register (BRR) ................................................................................. 279
10.3 Operation ........................................................................................................................ 288
10.3.1 Overview......................................................................................................... 288
10.3.2 Operation in Asynchronous Mode.................................................................. 290
10.3.3 Multiprocessor Communication ..................................................................... 299
10.3.4 Synchronous Operation .................................................................................. 306
10.4 SCI Interrupts.................................................................................................................. 315
10.5 Usage Notes .................................................................................................................... 316
Section 11 A/D Converter............................................................................................ 321
11.1 Overview ........................................................................................................................ 321
11.1.1 Features........................................................................................................... 321
11.1.2 Block Diagram................................................................................................ 322
11.1.3 Input Pins ........................................................................................................ 323
11.1.4 Register Configuration.................................................................................... 324
11.2 Register Descriptions...................................................................................................... 325
11.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ........................................ 325
11.2.2 A/D Control/Status Register (ADCSR) .......................................................... 326
11.2.3 A/D Control Register (ADCR) ....................................................................... 329
11.3 CPU Interface ................................................................................................................. 330
11.4 Operation ........................................................................................................................ 331
11.4.1 Single Mode (SCAN = 0) ............................................................................... 331
11.4.2 Scan Mode (SCAN = 1).................................................................................. 333
11.4.3 Input Sampling and A/D Conversion Time .................................................... 335
11.4.4 External Trigger Input Timing........................................................................ 336
11.5 Interrupts ........................................................................................................................ 337
11.6 Usage Notes .................................................................................................................... 337
Section 12 RAM ............................................................................................................. 339
12.1 Overview ........................................................................................................................ 339
12.1.1 Block Diagram................................................................................................ 339
12.1.2 Register Configuration.................................................................................... 340
12.2 System Control Register (SYSCR)................................................................................. 341
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