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HCPL-060L-060E Datasheet PDF : 20 Pages
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HCPL-260L/060L/263L/063L
High Speed LVTTL Compatible 3.3 Volt Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The HCPL-260L/060L/263L/063L are optically coupled
gates that combine a GaAsP light emitting diode and
an integrated high gain photo detector. An enable in-
put allows the detector to be strobed. The output of
the detector IC is an open collector Schottky-clamped
transistor. The internal shield provides a guaranteed
common mode transient immunity specification of
15 kV/μs at 3.3V.
This unique design provides maximum AC and DC circuit
isolation while achieving LVTTL/LVCMOS compati-bili-
ty. The optocoupler AC and DC operational parameters
are guaranteed from –40qC to +85qC allowing trouble-
free system performance.
x 3.3V/5V Dual Supply Voltages
x Low power consumption
x 15 kV/μs minimum Common Mode Rejection (CMR) at
VCM = 1000 V
x High speed: 15 MBd typical
x LVTTL/LVCMOS compatible
x Low input current capability: 5 mA
x Guaranteed AC and DC performance over tempera-
ture: –40qC to +85qC
x Available in 8-pin DIP, SOIC-8
x Strobable output (single channel products only)
These optocouplers are suitable for high speed logic
interfacing, input/output buffering, as line receivers in
environments that conventional line receivers cannot
tolerate and are recommended for use in extremely high
ground or induced noise environments.
x Safety approvals: UL, CSA, IEC/EN/DIN EN 60747-5-2
Applications
x Isolated line receiver
Functional Diagram
HCPL-260L/060L
NC 1
8 VCC
ANODE 2
7 VE
CATHODE 3
6 VO
NC 4
SHIELD
5 GND
x Computer-peripheral interfaces
x Microprocessor system interfaces
HCPL-263L/063L
x Digital isolation for A/D, D/A conversion
ANODE 1 1
CATHODE 1 2
8 VCC
x Switching power supply
7 VO1
x Instrument input/output isolation
CATHODE 2 3
6 VO2
x Ground loop elimination
ANODE 2 4
5 GND
SHIELD
x Pulse transformer replacement
TRUTH TABLE
(POSITIVE LOGIC)
LED ENABLE OUTPUT
ON
H
L
OFF
H
H
ON
L
H
OFF
L
H
ON
NC
L
OFF NC
H
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
x Field buses
A 0.1 μF bypass capacitor must be
connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
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