HD64F2667 Ver la hoja de datos (PDF) - Renesas Electronics

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HD64F2667

Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Renesas Electronics 

Item

9.3.9 Timer

Synchronous Register

(TSYR)

13.3.7 Serial Status

Register (SSR)

Page

288

406

13.3.9 Bit Rate

411

Register (BRR)

Table13.2

Relationships between

N Setting in BRR and

Bit Rate B

14.3.2 A/D

477

Control/Status Register

(ADCSR)

18.5.1 Notes on

540

Clock Pulse Generator

Section 19 Power- 544

Down Mode

Table 19.1 Operating

Mode

20.2 Register Bits

566

Revision (See Manual for Details)

Bit 7 and 6 initial value amended

(Before)  → (After) 0

Normal Serial Communication Interface Mode (When SMIF in

SCMR is 0)

Bit 2 Clearing condition amended

• When the DTC is activated by a TXI interrupt and writes data

to TDR

Table 13.2 amended

Mode

Smart Card

Interface Mode

Bit Rate

φ × 106

B=

S × 22n+1 × (N + 1)

Error

{ } Error (%) =

φ × 106

B × S × 22n+1 × (N + 1) – 1 × 100

Bit 7 Clearing condition amended

• When the DTC is activated by an ADI interrupt and ADDR is

read

Description amended

Note that the frequency of φ will be changed when setting

SCKCR or PLLCR while executing the external bus cycle with

the Write-data-buffer function.

EXDMAC and DMAC description deleted from table 19.1

Table amended

Register

Name

MRA

SAR

MRB

DAR

CRA

CRB

Bit 7

SM1

—

—

—

CHNE

—

—

—

—

—

—

—

Bit 6

SM0

—

—

—

DISEL

—

—

—

—

—

—

—

Bit 5

DM1

—

—

—

CHNS

—

—

—

—

—

—

—

Bit 4

DM0

—

—

—

—

—

—

—

—

—

—

—

Bit 3

MD1

—

—

—

—

—

—

—

—

—

—

—

Bit 2

MD0

—

—

—

—

—

—

—

—

—

—

—

Bit 1

DTS

—

—

—

—

—

—

—

—

—

—

—

Bit 0

Sz

—

—

—

—

—

—

—

—

—

—

—

Module

DTC*7

Rev. 3.00 Feb 22, 2006 page ix of xl

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