HD64F2667 Ver la hoja de datos (PDF) - Renesas Electronics
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HD64F2667 Datasheet PDF : 667 Pages
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Item
20.2 Register Bits
Page
573
574
575
20.3 Register Stated 576
in Each Operating
Mode
578
582
Revision (See Manual for Details)
Table amended
Register
Name
ADDRH
ADCSR
ADCR
DADR0
Bit 7
AD9
AD1
ADF
TRGS1
Bit7
Bit 6
AD8
AD0
ADIE
TRGS0
Bit6
Bit 5
AD7
—
ADST
SCANE
Bit5
Bit 4
AD6
—
—
SCANS
Bit4
Bit 3
AD5
—
CH3
CKS1
Bit3
Bit 2
AD4
—
CH2
CH3
Bit2
Bit 1
AD3
—
CH1
—
Bit1
Bit 0
AD2
—
CH0
—
Bit0
Module
A/D
D/A
Register
Name
FLMCR1
FLMCR2
EBR1
EBR2
Bit 7
—
FLER
EB7
—
Bit 6
SWE
—
EB6
—
Bit 5
ESU
—
EB5
EB13
Bit 4
PSU
—
EB4
EB12
Bit 3
EV
—
EB3
EB11
Bit 2
PV
—
EB2
EB10
Bit 1
E
—
EB1
EB9
Bit 0
P
—
EB0
EB8
Module
FLASH
(F-ZTAT
version )
Notes amended
Notes: 1. If the PCR setting specifies the same output trigger
for pulse output group 2 and pulse output group 3, the address
is H'FF4C. If the triggers are different, the NDRH address
corresponding to pulse output group 2 is H'FF4E and the NDRH
address corresponding to pulse output group 3 is H'FF4C. In
like manner, if the PCR setting specifies the same output trigger
for pulse output group 0 and pulse output group 1, the address
is H'FF4D. If the triggers are different, the NDRH address
corresponding to pulse output group 0 is H'FF4F and the NDRH
address corresponding to pulse output group 1 is H'FF4D.
2. Functions as C/A for SCI use, ...
3. Functions as CHR for SCI use, ...
4. Functions as STOP for SCI use, ...
5. Functions as MP for SCI use, ...
6. Functions as FER for SCI use, ...
7. Loaded in on-chip RAM. The bus width is 32 bits when the
DTC accesses this area as register information, and 16 bits
otherwise.
Note *1 deleted
(Before) SEMR*1 → (After) SEMR
(Before) RAMER*1 → (After) RAMER
(Before) FLMCR1*1 → (After) FLMCR1
(Before) FLMCR2*1 → (After) FLMCR2
(Before) EBR1*1 → (After) EBR1
(Before) EBR2*1 → (After) EBR2
Rev. 3.00 Feb 22, 2006 page xi of xl
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