Item
8.2.7 DTC Enable
Registers A to G
(DTCERA to DTCERG)
Page
299
14.3.9 Bit Rate Register 565,
(BRR)
566
Table 14.3 BRR Settings
for Various Bit Rates
(Asynchronous Mode)
Revision (See Manual for Details)
Table amended
… These bits are not automatically cleared when the DISEL bit
is 0 …
• When 0 is written to the DTCE bit after reading DTCE=1.
Table 14.3 amended
Bit Rate
(bit/s) n
9600
0
19200 0
31250 0
38400 —
8
Error
N (%) n
25 0.16 0
12 0.16 0
7
0.00 0
——
0
Operating Frequency (MHz)
9.8304
10
Error
Error
N (%) n N (%) n
31 0.00 0
32 –1.38 0
15 0.00 0
15 1.70 0
9
–1.73 0
9
0.00 0
7
0.00 0
7
1.70 0
12
Error
N (%)
38 0.16
19 –2.40
11 0.00
9 –2.40
Bit Rate
(bit/s) n
110
2
9600
0
19200 0
31250 0
12.288
Error
N (%) n
217 0.08 2
39 0.00 0
19 0.00 0
11 2.34 0
Operating Frequency (MHz)
14
14.7456
Error
Error
N (%) n N (%) n
248 –0.17 3
64 0.69 3
45 –0.94 0
47 0.00 0
22 –0.94 0
23 0.00 0
13 0.00 0
14 –1.73 0
16
Error
N (%)
70 0.03
51 0.16
25 0.16
15 0.00
Bit Rate
(bit/s) n
19200 0
31250 0
38400 0
17.2032
Error
N (%) n
27 0.00 0
16 1.20 0
13 0.00 0
Operating Frequency (MHz)
18
19.6608
Error
Error
N (%) n N (%) n
28 1.01 0
31 0.00 0
17 0.00 0
19 –1.73 0
14 –2.40 0 15 0.00 0
20
Error
N (%)
32 –1.38
19 0.00
15 1.70
566
Bit Rate
(bit/s) n
110
3
150
3
300
2
600
2
1200
1
2400
1
4800
0
9600
0
19200 0
31250 0
38400 0
25
Error
N (%) n
110 –0.02 3
80 0.47 3
162 –0.15 2
80 0.47 2
162 –0.15 1
80 0.47 1
162 –0.15 0
80 0.47 0
40 –0.76 0
24 0.00 0
19 1.70 0
Operating Frequency (MHz)
30
33
Error
Error
N (%) n N (%) n
132 0.13 3
145 0.33 3
97 –0.35 3
106 0.39 3
194 0.16 2
214 –0.07 2
97 –0.35 2
106 0.39 2
194 0.16 1 214 –0.07 1
97 –0.35 1
106 0.39 1
194 0.16 0 214 –0.07 0
97 –0.35 0
106 0.39 0
48 –0.35 0
53 –0.54 0
29 0
0
32 0
0
23 1.70 0
26 –0.54 0
34*
Error
N (%)
150 –0.05
110 –0.29
220 0.16
110 –0.29
220 0.16
110 –0.29
220 0.16
110 –0.29
54 0.61
33 0.00
27 –1.20
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Rev. 5.00 Aug 02, 2006 page ix of liv