Item
Page
14.3.9 Bit Rate Register 567
(BRR)
Table 14.4 Maximum Bit
Rate for Each Frequency
(Asynchronous Mode)
Table 14.5 Maximum Bit 568
Rate for Each Frequency
(Asynchronous Mode)
Revision (See Manual for Details)
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Table 14.6 BRR Settings 569
for Various Bit Rates
(Clocked Synchronous
Mode)
Table 14.7 Maximum Bit 570
Rate with External Clock
Input (Clocked
Synchronous Mode)
Table 14.8 Examples of 571
Bit Rate for Various BRR
Settings (Smart Card
Interface Mode) (when n =
0 and S = 372)
Table 14.9 Maximum Bit 572
Rate at Various
Frequencies (Smart Card
Interface Mode) (when S =
372)
14.8 IrDA Operation
618
Table 14.12 Settings of
Bits IrCKS2 to IrCKS0
15.3.1 I2C Bus Control 634
Register A (ICCRA)
Table 15.2 Transfer Rate
Note 1 amended
Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note 1 amended
Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Rev. 5.00 Aug 02, 2006 page x of liv