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GS9092 Datasheet PDF : 58 Pages
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GS9092 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type Description
47
DVB_ASI
Non
Input
Synchronous
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
When set HIGH by the application layer, the device will be configured
for the transmission of DVB-ASI data.The setting of the
SMPTE_BYPASS pin will be ignored.
When set LOW by the application layer, the device will not support the
encoding of DVB-ASI data.
49
SMPTE_BYPASS Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS / LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may
be enabled in this mode.
When set LOW, the device will not support the scrambling, encoding or
packet insertion of received SMPTE data. No I/O processing features
will be available and the device will enter a low-latency mode.
50
BLANK
Synchronous Input
with PCLK
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Functional only when chip is in SMPTE mode.
When set LOW by the application layer, the luma and chroma input
data is set to the appropriate blanking levels (TRS words will be
unaltered at all times)
When set HIGH by the application layer, the input data will pass into the
device unaltered.
51
DETECT_TRS
Non
Input
CONTOL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS / LVTTL compatible.
Used to select external H,V, and F timing mode or TRS extraction
timing mode.
When set LOW by the application layer, the device will extract all
internal timing from the supplied H, V, and F timing signals.
When set HIGH by the application layer, the device will extract all
internal timing from the TRS signals embedded in the supplied video
stream. The H, V, and F signals will become outputs that can be
accessed via the STAT[2:0] pins.
Both 8-bit and 10-bit TRS code words will be identified by the device.
52
FIFO_EN
Non
Input
Synchronous
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable / disable the internal FIFO.
When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will be
clocked into the device on the rising edge of the WR_CLK input pin if
the FIFO is in video mode or DVB-ASI mode.
When FIFO_EN is LOW, the internal FIFO is bypassed and parallel
data is clocked into the device on the rising edge of the PCLK input.
53
VCO_VDD
Analog
Input
Power
Power supply connection for Voltage-Controlled-Oscillator. Connect to
+1.8V DC.
54
LB_CONT
Analog
Input
CONTROL SIGNAL INPUT
Control voltage to fine-tune the loop bandwidth of the PLL.
28202 - 2 September 2005
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