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componentes Descripción

Fabricante

GS7025

PRO-LINX ™ GS7025 Serial Digital Receiver

Gennum -> Semtech 

provides a 100mVp-p signal when driving a 50Ω

oscilloscope input. Due to additional power consumed by

this diagnostic circuit, it is not recommended for continuous

operation.

2. RECLOCKER

The reclocker receives a differential serial data stream from

the internal multiplexer. It locks an internal clock to the

incoming data. It outputs the differential PECL retimed data

signal on SDO/SDO. It outputs the recovered clock on SCO/

SCO. The timing between the output and clock signals is

shown in Figure 9.

SDO

SCO

50%

2-2. VCO

The VCO is a differential low phase noise, factory trimmed

oscillator that provides increased immunity to PCB noise

and precise control of the VCO centre frequency. The VCO

has a pull range of ±15% about the centre frequency. A

single low impedance external resistor, RVCO, sets the VCO

centre frequency. The low impedance RVCO minimizes

thermal noise and reduces the PLL's sensitivity to PCB

noise.

The recommended RVCO value for SMPTE 259M-C

applications is 365Ω.

When the input data stream is removed for an excessive

period of time (see AC electrical characteristics table), the

VCO frequency can drift from the 270Mb/s centre frequency

to the limits shown in Table1.

TABLE 1: Frequency Drift Range

FREQUENCY

MIN (%)

MAX(%)

270Mb/s lock

-13

28

Fig. 9 Output and Clock Signal Timing

The reclocker contains three main functional blocks: the

Phase Locked Loop, Frequency Acquisition, and Logic

Circuit.

2-1. Phase Locked Loop (PLL)

The Phase Locked Loop locks the internal PLL clock to the

incoming data rate. A simplified block diagram of the PLL is

shown below. The main components are the VCO, the

phase detector, the charge pump, and the loop filter.

DDI/DDI 2

PHASE

DETECTOR

INTERNAL

PLL CLOCK

CHARGE

PUMP

VCO

LF+ LFS LF-

RVCO

RLF CLF1

CLF2

LOOP

FILTER

Fig. 10 Simplified Block Diagram of the PLL

2-3. Phase Detector

The phase detector compares the phase of the PLL clock

with the phase of the incoming data signal and generates

error correcting timing pulses. The phase detector design

provides a linear transfer function which maximizes the

input jitter tolerance of the PLL.

2-4. Charge Pump

The charge pump takes the phase detector output timing

pulses and creates a charge packet that is proportional to

the system phase error. A unique differential charge pump

design insures that the output phase does not drift when

data transitions are sparse. This makes the GS7025 ideal

for SMPTE 259M-C applications where pathological signals

have data transition densities of 0.05.

2-5. Loop Filter

The loop filter integrates the charge pump packets and

produces a VCO control voltage. The loop filter is

comprised of three external components which are

connected to pins LF+, LFS, and LF-. The loop filter design

is fully differential giving the GS7025 increased immunity to

PCB board noise.

The loop filter components are critical in determining the

loop bandwidth and damping of the PLL. Choosing these

component values is discussed in detail in the PLL DESIGN

GUIDELINES section. Recommended values for SMPTE

259M-C applications are shown in the Typical Application

Circuit. No further changes from the recommended GS7025

loop filter components are necessary.

9

GENNUM CORPORATION

522 - 80 - 00

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