GS7005 Ver la hoja de datos (PDF) - Gennum -> Semtech

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GS7005

Complete Serial Digital Video Receiver

Gennum -> Semtech 

7. SIGNAL LOCK DETECT

When there are no input data transitions, the CD pin goes to

a HIGH logic level and forces the VCO to the centre

frequency as described in section 5, PLL, MUX, and f/10.

This output can be used to control an external transistor

and LED. When there are input data transitions (valid or

invalid), the CD pins goes to a LOW logic state.

The locking state of the PLL is indicated by the output

LOCK signal being set to a logical HIGH level. This pin

however, may have periodic transitions to a LOW logic state

of 64µs maximum duration even though the device is

properly locked. The parallel data signal integrity is not

affected under these conditions. Therefore, the LOCK pin

should not be used as a logic control signal if a steady level

is required. The output voltage remains in a logic HIGH

state for a sufficient period and can be used to drive visual

indicators such as LEDs.

8. SERIAL TO PARALLEL CONVERTOR

The final function of the GS7005 is the serial-to-parallel

conversion. The output signals of the receiver are ten data

signals and one clock signal. The shift register is filled by

the serial data and read out at a positive edge of the read-

out signal. After parallel read out of the shift register, the

parallel data is sampled with the negative edge of the

27MHz clock to achieve synchronization.

10

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