GL800HT25 Ver la hoja de datos (PDF) - GENESYS LOGIC

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GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

LIST OF FIGURES

FIGURE 3.1 - SYSTEM DIAGRAM ......................................................................................... 8

FIGURE 3.2 - BLOCK DIAGRAM........................................................................................... 9

FIGURE 4.1 - PINOUT DIAGRAM ........................................................................................ 11

FIGURE 5.1 - TRANSMIT STATE DIAGRAM........................................................................ 15

FIGURE 5.2 - TIMING DIAGRAM OF TRANSMIT FOR DATA PACKET ................................ 16

FIGURE 5.3 - RECEIVE STATE DIAGRAM .......................................................................... 16

FIGURE 5.4 - TIMING DIAGRAM OF RECEIVE FOR DATA PACKET (WITH CRC-16) ....... 17

FIGURE 5.5 - CLK30 RISING AND FALLING EDGE VS. INPUT/OUTPUT SIGNALS........... 18

FIGURE 5.6 - RELATIONSHIP BETWEEN MODE CHANGE AND OTHER INPUT SIGNALS .. 19

FIGURE 6.1 - GL800HT25 48 PIN LQFP PACKAGE ........................................................ 20

LIST OF TABLES

TABLE 4.1 - PIN LIST ......................................................................................................... 12

TABLE 4.2 - PIN DESCRIPTIONS......................................................................................... 12

©2000-2003 Genesys Logic Inc.—All rights reserved.

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