GAL18V10 Ver la hoja de datos (PDF) - Lattice Semiconductor
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GAL18V10 Datasheet PDF : 14 Pages
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Power-Up Reset
Specifications GAL18V10
Vcc
Vcc (min.)
CLK
INTERNAL REGISTER
Q - OUTPUT
t su
t wl
t pr
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
Circuitry within the GAL18V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1μs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
conditions must be met to provide a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
Vcc
(Vref Typical = 3.2V)
Active Pull-up
Circuit
Vcc Vref Vcc
ESD
Protection
Circuit
PIN
PIN
Feedback
Tri-State
Control
Active Pull-up
Circuit
Vcc
Vref
(Vref Typical = 3.2V)
Data
Output
PIN
ESD
Protection
Circuit
Typical Input
Feedback
(To Input Buffer)
Typical Output
11
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