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GAL16V8Z

Zero Power E2CMOS PLD

Lattice Semiconductor 

Specifications GAL16V8Z

GAL16V8ZD

Simple Mode

In the Simple mode, macrocells are configured as dedicated inputs

or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the

common 10L8 and 12P6 devices with many permutations of ge-

neric output polarity or input choices.

Pins 1 and 11 are always available as data inputs into the AND

array. The center two macrocells (pins 15 & 16) cannot be used

in the input configuration.

Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It can-

not be used as functional input.

All outputs in the simple mode have a maximum of eight porduct The JEDEC fuse numbers including the UES fuses and PTD fuses

terms that can control the logic. In addition, each output has pro- are shown on the logic diagram.

grammable polarity.

Vcc

XOR

Combinatorial Output with Feedback Configuration

for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to

this function.

Vcc

XOR

Combinatorial Output Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- Pins 15 & 16 are permanently configured to this

function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to

this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

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