FX009ALG Ver la hoja de datos (PDF) - CML Microsystems Plc

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FX009ALG

Low-Noise Digitally Controlled Amplifier Array

CML Microsystems Plc 

The gain of each amplifier block (Channel 1 to Channel 8)

in the FX009A is set by a separate 8-bit data word ( bit 7

to bit 0 ). This 8-bit word, consisting of 4 Address bits (bit

7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded

to the Control Data Input in serial format using the external

data clock.

Data is loaded to the FX009A on the rising edge of the

Serial Clock. Loaded data is executed on the falling

(rising) edge of the Load/Latch (Load/Latch) pulse. Table

1 shows the format of each 4-bit Address word, Table 2

shows the format of each Gain Control word with Figure 4

describing the data loading operation and timing.

Table 1 Address Word Format

Table 2 Gain Control Word Format

Bit 7

MSB

1

1

1

1

1

1

1

1

Bit 6

0

0

0

0

1

1

1

1

Bit 5

0

0

1

1

0

0

1

1

Bit 4

LSB

0

1

0

1

0

1

0

1

Channel

Selected

1

2

3

4

5

6

7

8

Data Loading

The 8-bit data word is loaded bit 7 first and bit 0 last.

Bit 7 must be a logic “1” to address the chip.

If bit 7 in the word is a logic “0” that 8-bit word will not be

executed. Figure 4 (below) shows the timing information

required to load and operate this device.

Bit 3 Bit2 Bit 1 Bit 0 Stage 1 to 7 Stage 8

MSB

LSB (0.43dB)

(2.0dB)

0

0

0

0 Powersave Powersave

0

0

0

1

-3.0

-14.0 dB

0

0

1

0

-2.571

-12.0 dB

0

0

1

1

-2.143

-10.0 dB

0

1

0

0

-1.714

-8.0 dB

0

1

0

1

-1.286

-6.0 dB

0

1

1

0

-0.857

-4.0 dB

0

1

1

1

-0.428

-2.0 dB

1

0

0

0

0

0 dB

1

0

0

1

0.428

2.0 dB

1

0

1

0

0.857

4.0 dB

1

0

1

1

1.286

6.0 dB

1

1

0

0

1.714

8.0 dB

1

1

0

1

2.143

10.0 dB

1

1

1

0

2.571

12.0 dB

1

1

1

1

3.0

14.0 dB

SERIAL DATA CLOCK

SERIAL DATA IN

(ONE 8-BIT WORD)

t PWL

t DS

t PWH

tDH

Logic ’1’

Loaded

First

BIT 7

BIT 6 BIT 1

8th

Clock

Pulse

Loaded Last

BIT 0

LOAD/LATCH

LOAD/LATCH

t LLD

t LLW

Next

Clock

Pulse

t LLO

Timing

tPWH

Serial Clock "High" Pulse Width

tPWL

Serial Clock "Low" Pulse Width

Fig.4 Serial Control Data Loading Diagram

tDS

Data Set-up Time

tDH

Data Hold Time

4

tLLD

Load/Latch Delay

tLLW

Load/Latch Pulse Width

tLLO

Load/Latch Over Time

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