FX009A Ver la hoja de datos (PDF) - CML Microsystems Plc
Número de pieza
componentes Descripción
Fabricante
FX009A Datasheet PDF : 7 Pages
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Pin Number
FX009A FX009A
J
LG/LS
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
Function
Serial Clock : This external clock pulse input is used to “clock in” the Control Data.
See Figure 4, Data Load Timing. This input has an internal 1MΩ pullup resistor.
Load/Latch : Governs the loading and execution of the control data. During serial
data loading this input should be kept at a logical '0' to ensure that data rippling past
the latches has no effect. When all 8 bits have been loaded, this input should be
strobed '0' ⇒ '1' ⇒ '0' to latch the new data in. Data is executed on the falling edge
of the strobe. If the Load/Latch input is used this pin should be left open circuit. This
input has an internal 1MΩ pullup resistor.
Load/Latch : The inverted Load/Latch input. This function governs the loading and
execution of the control data. During serial data loading this input should be kept at a
logical '1' to ensure that data rippling past the latches has no effect. When all 8 bits
have been loaded, this input should be strobed '1' - '0' - '1' to latch the new data in.
Data is executed on the rising edge of the strobe. If the Load/Latch input is used this
pin should be left open circuit. This input has an internal 1MΩ pulldown resistor.
Ch1 Input :
Ch2 Input :
Ch3 Input :
Ch4 Input :
Analogue Inputs :
These individual amplifier inputs are self-biasing, a.c. input
analogue signals must be capacitively coupled to these pins,
as shown in Figure 2.
In the powersave modes the inputs are biased at VDD/2.
Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'
V : The output of the on-chip bias circuitry, held at V /2. This pin should be
BIAS
DD
decoupled to VSS as shown in Figure 2.
Ch5 Input :
Analogue Inputs :
Ch6 Input :
Ch7 Input :
Ch8 Input :
VSS : Negative supply rail (GND).
Ch8 Output :
Analogue Outputs :
Ch7 Output :
Ch6 Output :
Ch5 Output :
The individual "Gain Controlled" amplifier outputs.
Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps, Ch8
could be utilized as a volume control, ranging from -14dB to
+14dB in 2.0dB steps.
In the powersave mode the selected output is biased at VDD/2.
No internal connection. Do not use.
Ch4 Output :
Analogue Outputs
Ch3 Output :
Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'
Ch2 Output :
Ch1 Output :
V : Positive supply rail. A single +5-volt power supply is required.
DD
Control Data Input : Operation of the 8 amplifier channels (Ch1 – Ch8) is controlled
by the 8 bits of data entered serially at this pin . The data is entered (bit 7 to bit 0) on
the rising edge of the external Serial Clock. The data format is described in Tables 1,
2 and Figure 4. This input has an internal 1MΩ pullup resistor.
2
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