PEB2466-HV1.2 Ver la hoja de datos (PDF) - Infineon Technologies

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PEB2466-HV1.2

Four Channel Codec Filter with PCM- and µ-Controller Interface SICOFI®4-µC

Infineon Technologies 

PEB 2466

1.3 Pin Definition and Functions

Pin No. Symbol Input (I) Function

Output (O)

General Description

Common Pins for all Channels

24

VDDD

I

21

GNDD I

52

VDDA12

I

61

VDDA34

I

56

VREF

I/O

57

VDDREF

I

31

FSC

I

32

PCLK I

30

DRB

I

29

DXB

O

28

TCB

O

27

DRA

I

26

DXA

O

+ 5 V supply for the digital circuitry 1)

Ground Digital, not internally connected to

GNDA1,2,3,4

All digital signals are referred to this pin

+ 5 V Analog supply voltage for channel 1 and 2 1)

+ 5 V Analog supply voltage for channel 3 and 4 1)

Reference voltage, has to be connected to a 220 nF

cap. to ground, can also be used as virtual ground

for analog inputs and outputs (high-ohmic buffer

needed !!!)

+ 5 V Analog supply voltage (100 nF cap. required)

Frame synchronization clock, 8 kHz, identifies the

beginning of the frame, individual time slots are

referenced to this pin, FSC must be synchronous to

PCLK

Data clock 128 to 8192 kHz, determines the rate at

which PCM data is shifted into or out of the

PCM-ports

PCM-interface: Receive PCM data from

PCM-highway B, data for each channel is received

in 8 bit bursts every 125 µs

PCM-interface: Transmit PCM data to PCM-highway

B, data for each channel is transmitted in 8 bit burst

every 125 µs

PCM-interface: Transmit control output B, is active if

data is transmitted via DXB, active low, open drain

PCM-interface: Receive PCM data from

PCM-highway A, data for each channel is received

in 8 bit bursts every 125 µs

PCM-interface: Transmit PCM data to PCM-highway

A, data for each channel is transmitted in 8 bit burst

every 125 µs

Semiconductor Group

10

02.97

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