FT2232H Ver la hoja de datos (PDF) - Future Technology
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FT2232H Datasheet PDF : 67 Pages
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Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
3.2 FT2232H Pin Descriptions
This section describes the operation of the FT2232H pins. Both the LQFP and the QFN packages have the
same function on each pin. The function of many pins is determined by the configuration of the FT2232H.
The following table details the function of each pin dependent on the configuration of the interface. Each
of the functions are described in the following table (Note: The convention used throughout this
document for active low signals is the signal name followed by a #).
Pins marked ** default to tri-stated inputs with an internal 75KΩ (approx) pull up resistor to VCCIO.
Pin
Pin # Pin Name
16
ADBUS0
17
ADBUS1
18
ADBUS2
19
ADBUS3
21
ADBUS4
22
ADBUS5
23
ADBUS6
24
ADBUS7
26
ACBUS0
27
ACBUS1
28
ACBUS2
29
ACBUS3
30
ACBUS4
32
ACBUS5
33
ACBUS6
34
ACBUS7
38
BDBUS0
39
BDBUS1
40
BDBUS2
41
BDBUS3
43
BDBUS4
44
BDBUS5
45
BDBUS6
46
BDBUS7
48
BCBUS0
52
BCBUS1
53
BCBUS2
54
BCBUS3
55
BCBUS4
57
BCBUS5
58
BCBUS6
59
BCBUS7
60 PWREN#
ASYNC
Serial
(RS232)
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
TXDEN
**
**
RXLED#
TXLED#
**
**
**
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
TXDEN
**
**
RXLED#
TXLED#
**
**
PWRSAV
#
PWREN#
FT2232H
245 FIFO
SYNC
D0
D1
D2
D3
D4
D5
D6
D7
RXF#
TXE#
RD#
WR#
SIWUA
CLKOUT
OE#
**
PWRSAV
#
Pin functions (depends on configuration)
245 FIFO
D0
D1
D2
D3
D4
D5
D6
D7
RXF#
TXE#
RD#
WR#
SIWUA
**
**
**
ASYNC
Bit-bang
D0
D1
D2
D3
D4
D5
D6
D7
**
WRSTB#
RDSTB#
**
SIWUA
**
**
**
SYNC
Bit-bang
MPSSE
Channel A
D0
TCK/SK
D1
TDI/DO
D2
TDO/DI
D3
TMS/CS
D4
GPIOL0
D5
GPIOL1
D6
GPIOL2
D7
GPIOL3
**
GPIOH0
WRSTB# GPIOH1
RDSTB# GPIOH2
**
GPIOH3
SIWUA GPIOH4
**
GPIOH5
**
GPIOH6
**
GPIOH7
Fast
Serial
interface
USES
CHANNEL
B
D0
D1
D2
D3
D4
D5
D6
D7
RXF#
TXE#
RD#
WR#
SIWUB
**
**
PWRSAV
#
D0
D1
D2
D3
D4
D5
D6
D7
**
WRSTB#
RDSTB#
**
SIWUB
**
**
PWRSAV
#
Channel B
D0
TCK/SK
D1
TDI/DO
D2
TDO/DI
D3
TMS/CS
D4
GPIOL0
D5
GPIOL1
D6
GPIOL2
D7
GPIOL3
**
GPIOH0
WRSTB# GPIOH1
RDSTB# GPIOH2
**
GPIOH3
SIWUB GPIOH4
**
GPIOH5
**
GPIOH6
PWRSAV
#
GPIOH7
FSDI
FSCLK
FSDO
FSCTS
SIWUB
PWRSAV
#
CPU
Style
FIFO
Host Bus
Emulation
D0
D1
D2
D3
D4
D5
D6
D7
CS#
A0
RD#
WR#
SIWUA
**
**
**
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
CS#
A0
RD#
WR#
SIWUB
**
**
PWRSAV#
CS#
ALE
RD#
WR#
IORDY
CLKOUT
I/O0
I/O1
**
**
**
**
**
**
**
PWRSAV#
PWREN# PWREN# PWREN# PWREN# PWREN# PWREN# PWREN# PWREN#
Copyright © 2012 Future Technology Devices International Limited
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