FSL127H Ver la hoja de datos (PDF) - Fairchild Semiconductor
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FSL127H Datasheet PDF : 15 Pages
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Functional Description
Startup Operation
For startup, the HV pin is connected to the line input or
bulk capacitor through the external resistor RHV, as
shown in Figure 23. Typical startup current drawn from
the HV pin is 3.5mA and it charges the VDD capacitor
through the resistor RHV. The startup current turns off
when the VDD capacitor voltage reaches VDD-ON. The
VDD capacitor maintains VDD until the auxiliary winding
of the transformer provides the operating current.
CDC
R HV
AC line
HV
VDD
FSL127H
DDD
NA
CDD
Figure 23. Startup Circuit
Green-Mode Operation
The FSL127H uses feedback voltage (VFB) as an
indicator of the output load and modulates the PWM
frequency, as shown in Figure 25, such that the
switching frequency decreases as load decreases. In
heavy load conditions, the switching frequency is
100kHz. Once VFB decreases below VFB-N (2.5V), the
PWM frequency starts to linearly decrease from 100kHz
to 18kHz to reduce the switching losses. As VFB
decreases below VFB-G (2.4V), the switching frequency
is fixed at 18kHz and FSL127H enters “deep” green
mode to reduce the standby power consumption. As
VFB decreases below VFB-ZDC (2.1V), FSL127H enters
burst-mode operation. When VFB drops below VFB-ZDC,
FSL127H stops switching and the output voltage starts
to drop, which causes the feedback voltage to rise.
Once VFB rises above VFB-ZDC, switching resumes. Burst
mode alternately enables and disables switching,
thereby reducing switching loss to improve power
saving, as shown in Figure 26.
Slope Compensation
FSL127H is designed for flyback power converter. The
peak-current-mode control is used to optimize system
performance. Slope compensation is added to stabilize
the current loop. The FSL127H inserts a synchronized,
positively sloped ramp at each switching cycle.
Soft Start
The FSL127H has internal soft-start circuit that slowly
increases the SenseFET current after startup. The
typical soft-start time is 5ms, during which the VLimit
level is increased in six steps to smoothly establish the
required output voltage, as shown in Figure 24. It also
helps prevent transformer saturation and reduces stress
on the secondary diode during startup.
Figure 25. PWM Frequency
Figure 24. Soft-Start Function
Figure 26. Burst Mode Operation
© 2010 Fairchild Semiconductor Corporation
FSL127H • Rev. 1.0.2
10
www.fairchildsemi.com
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