FSD200 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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componentes Descripción

Fabricante

FSD200

Green Mode Fairchild Power Switch (FPS™)

Fairchild Semiconductor 

FSD210, FSD200

Functional Description

1. Startup : At startup, the internal high voltage current

source supplies the internal bias and charges the external

Vcc capacitor as shown in figure 7. In the case of the

FSD210, when Vcc reaches 8.7V the device starts switching

and the internal high voltage current source is disabled (see

figure 1). The device continues to switch provided that Vcc

does not drop below 6.7V. For FSD210, after startup, the

bias is supplied from the auxiliary transformer winding. In

the case of FSD200, Vcc is continuously supplied from the

external high voltage source and Vcc is regulated to 7V by

an internal high voltage regulator (HVReg), thus eliminating

the need for an auxiliary winding (see figure 2).

Vin,dc

Istr

Vstr

i = Istr-max 100uA

i = Istr-max

100uA

Vcc

max

100uA

J-FET

UVLO

Vref FSD2xx

Vcc

Vin,dc

Vin,dc

Istr

Istr

Vstr

Vcc

L

8.7V/

6.7V

H

FSD210

Vstr

Vcc

HV

Reg.

7V

FSD200

Figure 6. Internal startup circuit

Calculating the Vcc capacitor is an important step to design-

ing in the FSD200/210. At initial start-up in both the

FSD200/210, the stand-by maximum current is 100uA, sup-

plying current to UVLO and Vref Block. The charging cur-

rent (i) of the Vcc capacitor is equal to Istr - 100uA. After

Vcc reaches the UVLO start voltage only the bias winding

supplies Vcc current to device. When the bias winding volt-

age is not sufficient, the Vcc level decreases to the UVLO

stop voltage. At this time Vcc oscillates. In order to prevent

this ripple it is recommended that the Vcc capacitor be sized

between 10uF and 47uF.

UVLO

start

UVLO

stop

Vcc must not drop

to UVLO stop

Auxiliary winding

voltage

t

Figure 7. Charging the Vcc capacitor through Vstr

3. Leading edge blanking (LEB) : At the instant the inter-

nal Sense FET is turned on, there usually exists a high cur-

rent spike through the Sense FET, caused by the primary side

capacitance and secondary side rectifier diode reverse recov-

ery. Exceeding the pulse-by-pulse current limit could cause

premature termination of the switching pulse (see Protection

Section). To counter this effect, the FPS employs a leading

edge blanking (LEB) circuit. This circuit inhibits the over

current comparator for a short time (TLEB) after the Sense

FET is turned on.

2. Feedback Control : The FSD200/210 are both voltage

mode devices as shown in Figure 8. Usually, a H11A817

optocoupler and KA431 voltage reference (or a FOD2741

integrated optocoupler and voltage reference) are used to

implement the isolated secondary feedback network. The

feedback voltage is compared with an internally generated

sawtooth waveform, directly controlling the duty cycle.

When the KA431 reference pin voltage exceeds the internal

reference voltage of 2.5V, the optocoupler LED current

increases pulling down the feedback voltage and reducing

the duty cycle. This event will occur when either the input

voltage increases or the output load decreases.

OSC

Vcc Vref

5uA

0.25mA

Vo

Vfb FB

4

Gate

driver

Cfb

R

KA431

VSD

OLP

Figure 8. PWM and feedback circuit

4. Protection Circuit : The FSD200/210 has 2 self protec-

tion functions: over load protection (OLP) and thermal shut-

down (TSD). Because these protection circuits are fully

integrated into the IC with no external components, system

9

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