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Fabricante

FS6131

Programmable Line Lock Clock Generator IC

ON Semiconductor 

FS6131

4.1.4. Post Divider

The post divider consists of three individually programmable dividers, as shown in Error! Reference source not found..

fGBL

POST1[1:0]

POST2[1:0]

POST3[1:0]

Post

Divider 1

(NP1)

Post

Divider 2

(NP2)

Post

Divider 3

(NP3)

POST DIVIDER (NPx)

Figure 4: Post Divider

fout

The moduli of the individual dividers are denoted as NP1, NP2, and NP3, and together they make up the array modulus NPx.

N Px = N P1 × N P2 × N P3

The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to

the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to

fCLK

=

f REF

⎜⎜⎝⎛

NF

NR

⎟⎟⎠⎞⎜⎜⎝⎛

1

N Px

⎟⎟⎠⎞

The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies

must be achieved exactly.

Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.

4.2 Phase Adjust and Sampling

In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock.

Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input

clock. Every cycle of the input clock equals NR/NF cycles of the VCO clock.

fIN

Reference

Divider (NR)

fIN

fOUT

Phase

Frequency

Detect

VCO

Feedback

Divider (NF)

Figure 5: Simple PLL

fOUT

The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because

the post divider is outside the feedback loop.

Rev. 4 | Page 5 of 44 | www.onsemi.com

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