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APU428 Ver la hoja de datos (PDF) - APLUS INTEGRATED CIRCUITS

Número de pieza
componentes Descripción
Fabricante
APU428
Aplus
APLUS INTEGRATED CIRCUITS Aplus
APU428 Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
APU428
Pad No.
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Pad Name
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
X
1970
1970
1970
1970
1970
1970
1970
1970
1970
1970
1970
1840
1710
1595
Y
995
1110
1225
1340
1455
1570
1685
1800
1915
2045
2175
2265
2265
2265
Pad No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Pad Name
X
Y
INT
70
1340
IOM1
70
1225
IOM2
70
1110
IOM3
70
995
IOM4
70
880
VDD1
70
765
VDD2
70
650
VDD3
70
535
CUP1
70
420
CUP2
70
290
COM1
70
160
COM2
200
70
COM3
330
70
COM4
445
70
Chip size: 84.65 x 96.45 mil2
Pad Descriptions
Pad Name
I/O
BAK
VDD1
VDD2
VDD3
RESET
I
INT
I
TESTA
I
CUP1
O
CUP2
XIN
XOUT
I
O
CFIN
I
CFOUT
O
COM1~4
O
SEG1~42
O
IOA1~4
I/O
Description
Positive back-up voltage.
In Li mode, connects a 0.1u capacitance to GND.
LCD drives the voltage and positive supply voltage.
While in Ag mode, connects +1.5V to VDD1.
While in Li/ExtV mode, connects +3.0V to VDD2.
Input pin from LSI reset request signal.
Internal pull-down resistor.
Input pin for external INT request signal.
Falling or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or none is selected by mask option.
Test signal input pin.
Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3 pins.
Connects the CUP1 and CUP2 pins with nonpolarized electrolytic capacitor if
1/2 or 1/3 bias mode has been selected.
In the static mode, these pins should be open.
Time-based counter frequency (clock-specified, LCD alternating frequency,
alarm signal frequency) or system clock oscillation. 32kHz crystal oscillator.
Oscillation stops at the execution of STOP instruction.
System clock oscillation.
Connected with ceramic resonator.
Connected with RC oscillation circuit.
Oscillation stops at the execution of STOP or SLOW instruction.
Output pins for supplying voltage to drive the common pins of the LCD or LED
panel.
Output pins for LCD or LED panel segment.
Input/Output port A can use software to define the internal pull-low resistor and
chattering clock in order to reduce input bounce and generate interrupt.
This port shares pins with SEG37~40 and is set by mask option.
This port also shares pins with CC, RR, RT and RH, and is set by mask option.
Preliminary
4
Ver. 0.0

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