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FOD8001R2

High Noise Immunity, 3.3V/5V Logic Gate Optocoupler

Fairchild Semiconductor 

December 2010

FOD8001

High Noise Immunity, 3.3V/5V Logic Gate Optocoupler

Features

■ High Noise Immunity characterized by Common Mode

Rejection (CMR) and Power Supply Rejection (PSR)

specifications

– 20kV/µs Minimum Static CMR @ Vcm = 1000V

– 25kV/µs Typical Dynamic CMR @ Vcm = 1500V,

20MBaud Rate

– PSR in excess of 10% of the supply voltages

across full operating bandwidth

■ High Speed:

– 25Mbit/sec Date Rate (NRZ)

– 40ns max. Propagation Delay

– 6ns max. Pulse Width Distortion

– 20ns max. Propagation Delay Skew

■ 3.3V and 5V CMOS Compatibility

■ Extended industrial temperate range, -40°C to 105°C

temperature range

■ Safety and regulatory pending approvals:

– UL1577, 3750 VACRMS for 1 min.

– IEC60747-5-2 (pending)

Applications

■ Industrial fieldbus communications

– Profibus, DeviceNet, CAN, RS485

■ Programmable Logic Control

■ Isolated Data Acquisition System

Description

The FOD8001 is a 3.3V/5V high-speed logic gate

Optocoupler, which supports isolated communications

allowing digital signals to communicate between sys-

tems without conducting ground loops or hazardous

voltages. It utilizes Fairchild’s proprietary coplanar pack-

aging technology, Optoplanar®, and optimized IC design

to achieve high noise immunity, characterized by high

common mode rejection and power supply rejection

specifications.

This high-speed logic gate optocoupler, packaged in a

compact 8-pin small outline package, consists of a high-

speed AlGaAs LED driven by a CMOS buffer IC coupled

to a CMOS detector IC. The detector IC comprises an

integrated photodiode, a high-speed transimpedance

amplifier and a voltage comparator with an output driver.

The CMOS technology coupled to the high efficiency of

the LED achieves low power consumption as well as

very high speed (40ns propagation delay, 6ns pulse

width distortion).

Related Resources

■ www.fairchildsemi.com/products/opto/

■ www.fairchildsemi.com/pf/FO/FOD0721.html

■ www.fairchildsemi.com/pf/FO/FOD0720.html

■ www.fairchildsemi.com/pf/FO/FOD0710.html

Functional Schematic

VDD1 1

8 VDD2

VI 2

7 NC

*3

6 VO

GND1 4

5 GND2

*: Pin 3 must be left unconnected

©2008 Fairchild Semiconductor Corporation

FOD8001 Rev. 1.0.3

Truth Table

VI LED VO

H OFF H

L ON L

www.fairchildsemi.com

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