FM31276 Ver la hoja de datos (PDF) - Ramtron International Corporation

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FM31276

5V Integrated Processor Companion with Memory

Ramtron International Corporation 

The calibration setting is stored in F-RAM so is not

lost should the backup source fail. It is accessed with

bits CAL.4-0 in register 01h. This value only can be

written when the CAL bit is set to a 1. To exit the

calibration mode, the user must clear the CAL bit to a

0. When the CAL bit is 0, the CAL/PFO pin will

revert to the power fail output function.

Crystal Oscillator

The crystal oscillator is designed to use a 12.5pF

crystal without the need for external components,

such as loading capacitors. The FM3127x device has

built-in loading capacitors that match the crystal.

If a 32.768kHz crystal is not used, an external

oscillator may be connected to the FM3127x. Apply

the oscillator to the X1 pin. Its high and low voltage

levels can be driven rail-to-rail or amplitudes as low

as approximately 500mV p-p. To ensure proper

operation, a DC bias must be applied to the X2 pin.

It should be centered between the high and low levels

on the X1 pin. This can be accomplished with a

voltage divider.

In the example, R1 and R2 are chosen such that the

X2 voltage is centered around the X1 oscillator drive

levels. If you wish to avoid the DC current, you may

FM31278/276/274/272 - 5V I2C Companion

choose to drive X1 with an external clock and X2

with an inverted clock using a CMOS inverter.

FM3127x

X1 X2

Vdd

R1

R2

Figure 8. External Oscillator

Layout Requirements

The X1 and X2 crystal pins employ very high

impedance circuits and the oscillator connected to

these pins can be upset by noise or extra loading. To

reduce RTC clock errors from signal switching noise,

a guard ring must be placed around these pads and

the guard ring grounded. SDA and SCL traces should

be routed away from the X1/X2 pads. The X1 and X2

trace lengths should be less than 5 mm. The use of a

ground plane on the backside or inner board layer is

preferred. See layout example. Red is the top layer,

green is the bottom layer.

VDD

SCL

SDA

X2

X1

PFI

VBAK

Layout for Surface Mount Crystal

(red = top layer, green = bottom layer)

VDD

SCL

SDA

X2

X1

PFI

VBAK

Layout for Through Hole Crystal

(red = top layer, green = bottom layer)

Rev. 2.0

Dec. 2007

Page 8 of 25

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