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MSC23409CL-70DS9 Ver la hoja de datos (PDF) - Oki Electric Industry

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MSC23409CL-70DS9 Datasheet PDF : 13 Pages
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MSC23409C/CL-xxDS9
Notes:
1. A start-up delay of 200 µs is required after power-up followed by a minimum of
eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before
proper device operation is achieved.
When using the internal refresh counter, a minimum of eight CAS before RAS
initialization cycles is required.
2. AC mesurement assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times are measured between VIH and VIL.
4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD
(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD
(Max.) limit, access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD
(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD
(Max.) limit, access time is controlled by tAA.
7. tOFF (Max.) defines the time at which the output achieves an open circuit condition
and is not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. RA10,
CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data
output pin will indicate a high level. If any internal bits are not equal, then data
output pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operational
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
10. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
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