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AM27C4096

4 Megabit (256 K x 16-Bit) CMOS EPROM

Advanced Micro Devices 

AC CHARACTERISTICS

Parameter Symbols

JEDEC Standard

Description

Test Setup

tAVQV

tELQV

tGLQV

tEHQZ

tGHQZ

tACC

tCE

tOE

tDF

(Note 2)

Address to Output Delay

CE#,

OE# = VIL

Max

Chip Enable to Output Delay

OE# = VIL Max

Output Enable to Output Delay

CE# = VIL Max

Chip Enable High or Output Enable

High to Output High Z, Whichever

Max

Occurs First

Output Hold Time from Addresses,

tAXQX

tOH CE# or OE#, Whichever Occurs

Min

First

Am27C4096

-95 -105 -120 -150 -200 -255 Unit

90 100 120 150 200 250 ns

90 100 120 150 200 250 ns

50 50 50 65 75 75 ns

30 30 40 40 40 60 ns

0 0 0 0 0 0 ns

Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.

Notes:

1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS

2.4

Addresses

0.45

2.0

0.8

Addresses Valid

2.0

0.8

CE#/PGM#

tCE

OE#

Output

High Z

tOE

tACC

(Note 1)

tOH

Valid Output

tDF (Note 2)

High Z

11408F-9

Notes:

1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC.

2. tDF is specified from OE# or CE#, whichever occurs first.

PACKAGE CAPACITANCE

Parameter

Symbol

Parameter

Description

Test Conditions

CIN

Input Capacitance VIN = 0

COUT

Output Capacitance VOUT = 0

Notes:

1. This parameter is only sampled and not 100% tested.

2. TA = +25°C, f = 1 MHz.

CDV040

PD 040

PL 044

Typ Max Typ Max Typ Max Unit

10

13

6

8

10

13

pF

10

13

8

10

12

14

pF

10

Am27C4096

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