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AS4SD4M16

4 Meg x 16 SDRAM Synchronous DRAM Memory

Austin Semiconductor 

Austin Semiconductor, Inc.

SDRAM

AS4SD4M16

CAS Latency

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability of the

first piece of output data. The latency can be set to two or three

clocks.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock edge

n+m. The DQs will start driving as a result of the clock edge one

cycle earlier (n + m - 1), and provided that the relevant access

times are met, the data will be valid by clock edge n + m. For

example, assuming that the clock cycle time is such that all

relevant access times are met, if a READ command is registered

at T0 and the latency is programmed to two clocks, the DQs will

start driving after T1 and the data will be valid by T2, as shown

in Figure 2. Table 2 below indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown op-

eration or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting

M7and M8 to zero; the other combinations of values for M7

and M8 are reserved for future use and/or test modes. The

programmed burst length applies to both READ and WRITE

bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with future ver-

sions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-

M2 applies to both READ and WRITE bursts; when M9 = 1,

the programmed burst length applies to READ bursts, but write

accesses are single-location (nonburst) accesses.

T0

T1

T2

T3

CLK

COMMAMD 111111112222222233333333 READ 111122223333 NOP 111122223333 NOP 111122223333

tLZ

tOH

DQ

tAC 11111222221111133333222221111133222223331111333332222

DOUT

111122223333

Table 2

CAS LATENCY

ALLOWABLE OPERATING FREQUENCY

(MHz)

SPEED CAS LATENCY = 2

-8

≤ 83

-10

≤ 66

CAS LATENCY = 3

≤ 125

≤ 100

CAS Latency = 2

T0

T1

T2

T3

T4

CLK

COMMAMD 11112222333344445555READ 111122223333

DQ

NOP 111122223333

NOP 111122223333 NOP 111122223333

tLZ

11111222221111133333222221111144444221111122233222223331111133333

tOH

DOUT

11111222223333344444

tAC

CAS Latency = 3

Figure 2

CAS LATENCY

111222333

111222333

UNDEFINED

DON’T CARE

AS4SD4M16

Rev. 2.1 6/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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