FAN6982MY Ver la hoja de datos (PDF) - Fairchild Semiconductor
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Fabricante
FAN6982MY Datasheet PDF : 16 Pages
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Electrical Characteristics (Continued)
Unless otherwise noted; VDD=15V, TA= 25°C, TA=TJ, RT=27kΩ, and CT=1000pF.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Gain Modulator
IAC
Input for AC Current
GAIN
Gain Modulator(3)(4)
BW
VO(GM)
Bandwidth
Output Voltage=5.7kΩ ×
(ISENSE-IOFFSET)
Multiplier Linear Range
IIAC=17.67µA, VVRMS=1.080V
VFBPFC=2.25V, at TA=25°C
IIAC=20µA, VVRMS=1.224V
VFBPFC=2.25V, at TA=25°C
IIAC=25.69µA, VVRMS=1.585V
VFBPFC=2.25V, at TA=25°C
IIAC=51.62µA, VVRMS=3.169V
VFBPFC=2.25V, at TA=25°C
IIAC=62.23µA, VVRMS=3.803V
VFBPFC=2.25V, at TA=25°C
IIAC=40µA
IAC=20µA, VRMS=1.224V
VFBPFC=2.25V, at TA=25°C
0
100 µA
7.500 9.000 10.500
6.367 7.004 7.704
3.801 4.182 4.600
0.950 1.045 1.149
0.660 0.726 0.798
2
kHz
0.710 0.798 0.885 V
PFC ILIMIT Comparator
VPFC-ILIMIT
Peak Current Limit
Threshold Voltage
Cycle-by-Cycle Limit
-1.25 -1.15 -1.05 V
△Vpk
PFC ILIMIT-Gain Modulator
Output
IIAC=17.67µA, VVRMS=1.08V
VFBPFC=2.25V, at TA=25°C
200
mV
PFC Output Driver
VGATE-CLAMP
Gate Output Clamping
Voltage
VDD=22V
13
15
17
V
VGATE-L
VGATE-H
tR
Gate Low Voltage
Gate High Voltage
Gate Rising Time
VDD=15V; IO=100mA
VDD=13V; IO=100mA
VDD=15V; CL=4.7nF;
O/P= 2V to 9V
1.5
V
8
V
40
70 120 ns
tF
Gate Falling Time
VDD=15V; CL=4.7nF;
O/P= 9V to 2V
40
60 110 ns
DPFC-MAX
DPFC-MIN
Maximum Duty Cycle
Minimum Duty Cycle
VIEA<1.2V
VIEA>4.5V
94
97
%
0
%
Tri-Fault Detect
tFBPFC_OPEN Time to FBPFC Open
VFBPFC=VFBPFC-OVP to FBPFC
OPEN, 470pF from FBPFC to GND
2
4
ms
VPFC-UVP
PFC Feedback Under-
Voltage Protection
0.4
0.5 0.6
V
Notes:
3. This parameter, although guaranteed by design, is not 100% production tested.
4. This gain is the maximum gain of modulation with a given VRMS voltage when VEA is saturated to high.
© 2009 Fairchild Semiconductor Corporation
FAN6982 • Rev. 1.0.1
8
www.fairchildsemi.com
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