FAN4800AU Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
FAN4800AU Datasheet PDF : 19 Pages
| |||
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=15V, TA= 25°C, TA=TJ, RT=6.8kΩ, and CT=1000pF.
Symbol
Parameter
Condition
Min. Typ. Max.
PFC Output Driver
VGATE-CLAMP
VGATE-L
VGATE-H
Gate Output Clamping Voltage
Gate Low Voltage
Gate High Voltage
tR
Gate Rising Time
VDD=22V
VDD=15V, IO=100mA
VDD=13V, IO=100mA
VDD=15V, CL=4.7nF,
O/P= 2V to 9V
13
15
17
1.5
8
40
70 120
tF
Gate Falling Time
VDD=15V, CL=4.7nF,
O/P=9V to 2V
40
60 110
DPFC-MAX Maximum Duty Cycle
DPFC-MIN Minimum Duty Cycle
PWM ILIMIT Comparator
VPWM-ILIMIT Threshold Voltage
tPD
Propagation Delay to Output
tPWM-BNK Leading-Edge Blanking Time
PWM Output Driver
VIEA<1.2V
VIEA>4.5V
94
97
0
0.95 1.00 1.05
250
170 250 350
VGATE-CLAMP
VGATE-L
VGATE-H
Gate Output Clamping Voltage
Gate Low Voltage
Gate High Voltage
tR
Gate Rising Time
VDD=22V
VDD=15V, IO=100mA
VDD=13V, IO=100mA
VDD=15V, CL=4.7nF,
O/P=2V to 9V
18
19
20
1.5
8
30
60 120
tF
Gate Falling Time
VDD=15V, CL=4.7nF,
O/P=9V to 2V
30
50 110
DPWM-MAX
VPWM-LS
Soft-Start
Maximum Duty Cycle
PWM Comparator Level Shift
49.0 49.5 50.0
1.3 1.5 1.8
VSS-MAX
ISS
Brownout
Maximum Voltage
Soft-Start Current
VDD=15V
9.5 10.0 10.5
10
VRMS-UVL VRMS Threshold LOW
VRMS-UVH VRMS Threshold HIGH
△VRMS-UVP Hysteresis
tUVP
Under- Voltage Protection Delay
Sagging Protection
1.00 1.05 1.10
1.85 1.90 1.95
750 850 950
750 1000 1250
VRMS-SAG VRMS Threshold SAG LOW
0.80 0.85 0.90
tSAG
SAG Protection Delay
28
33
38
Notes:
3. This parameter, although guaranteed by design, is not 100% production tested.
4. This gain is the maximum gain of modulation with a given VRMS voltage when VVEA is saturated to HIGH.
Unit
V
V
V
ns
ns
%
%
V
ns
ns
V
V
V
ns
ns
%
V
V
µA
V
V
mV
ms
V
ms
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.0.0
9
www.fairchildsemi.com
Share Link: 