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componentes Descripción

Fabricante

FAN4800AU

PFC/ PWM Controller Combination

Fairchild Semiconductor 

Voltage Control of Boost Stage

The voltage-control loop regulates PFC output voltage

using an internal error amplifier such that the FB

voltage is the same as the internal reference of 2.5V.

Brownout Protection

The built-in internal brownout protection comparator

monitors the voltage of the VRMS pin. Once VRMS pin

voltage is lower than 1.05V, the PFC stage is shut down

to protect the system from over current.

FAN4800AU/CU starts up the boost stage once VRMS

voltage increases above 1.9V.

TriFault Detect™

To improve power supply reliability, reduce system

component count, and simplify compliance to UL 1950

safety standards, the FAN4800AU/CU includes

Fairchild’s TriFault Detect technology.

In a feedback path failure, the output voltage of the PFC

can exceed safe operating limits. TriFaultDetect

protects the power supply from a failure related to the

output feedback by monitoring the FBPFC voltage.

TriFaultDetect is an entirely internal circuit. It requires

no external components to serve its protective function.

VBOUT

Disable OPFC

RFB1

RFB2

0.5V +

VDD

-

300nA

+

FBPFC 2.75V -

TriFaultDetect

Figure 34. TriFault Detect™

PWM Stage

The PWM stage is capable of Current Mode or Voltage

Mode operation. In Current-Mode, the PWM ramp

(RAMP) is usually derived directly from a current-

sensing resistor or current transformer in the primary

side of the output stage, and is thereby representative

of the current flowing in the converter’s output stage.

ILIMIT, which provides cycle-by-cycle current limiting, is

typically connected to RAMP in such applications.

For Voltage-Mode operation, RAMP can be connected to

a separate RC timing network to generate a voltage ramp

against which the FBPWM voltage is compared. Under

these conditions, the voltage feed-forward from the PFC

bus can be used for better line transient response.

No voltage error amplifier is included in the PWM stage,

as this function is generally performed by KA431, in the

secondary side. To facilitate the design of opto-coupler

feedback circuitry, an offset voltage is built into the

inverting input of PWM comparator. This allows

FBPWM to command a zero percent duty cycle when

its pin voltage is below 1.5V.

VBOUT

RRAMP

CRAMP

REF

RAMP

1.5V

PWM

-

+

FBPWM

Figure 35. PWM Ramp Generation Circuit

PWM Current Limit

The ILIMIT pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. If the input voltage

at this pin exceeds 1V, the output of the PWM is

disabled for until the start of the next PWM clock cycle.

VIN OK Comparator

The VIN OK comparator monitors the output of the PFC

stage and inhibits the PWM stage if this voltage is less

than 2.4V (96% of its nominal value). Once this voltage

goes above 2.4V, the PWM stage begins soft-start. The

PWM stage is shut down when FBPFC voltage drops

below 1.3V.

PWM Soft-Start (SS)

PWM startup is controlled by the soft-start capacitor. A

current source of 10µA supplies the charging current for

the soft-start capacitor. PWM startup is prohibited until

the soft-start capacitor voltage reaches 1.5V.

© 2011 Fairchild Semiconductor Corporation

FAN4800AU/CU • Rev. 1.0.0

15

www.fairchildsemi.com

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