FAN4800AU Ver la hoja de datos (PDF) - Fairchild Semiconductor
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FAN4800AU Datasheet PDF : 19 Pages
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Functional Description
Oscillator
The internal oscillator frequency is determined by the
timing resistor and capacitor on the RT/CT pins as
shown in Figure 25. The frequency of the internal
oscillator is given:
f OSC
0.56 RT
1
CT
360CT
(1)
Because the PWM stage generally uses a forward
converter, it is necessary to limit the maximum duty
cycle at 50%. To have a small tolerance of the
maximum duty cycle, a frequency divider with toggle
flip-flops is used, as illustrated in Figure 25. The
operation frequency of PFC and PWM stage is 1/4 of
oscillator frequency. (For FAN4800CU, the operation
frequencies for PFC and PWM stages are 1/4 and 1/2
of oscillator frequency, respectively).
The dead time for the PFC gate drive signal is
determined by:
tDEAD 360CT
(2)
The dead time should be smaller than 2% of the
switching period to minimize line current distortion
around the line zero crossing.
Figure 25. Oscillator Configuration
VG.PFC
VG.PFC
VG.PWM
ID
IDS
VG.PWM
ID
IDS
Figure 27. Interleaved Leading / Trailing
Edge Modulation
Figure 27 shows the interleaved leading / trailing edge
modulation, where the turn-off of the PFC drive signal is
synchronized to the turn-on of the PWM drive signal.
This technique allows the PFC output diode current to
flow directly into the downstream DC/DC converter,
minimizing the current ripple of PFC output capacitor.
Gain Modulator
Gain modulator is the key block for the PFC stage
because it provides the reference to the current control
error amplifier for the input current shaping, as shown in
Figure 28. The output current of the gain modulator is a
function of VEA, IAC, and VRMS. The gain of the gain
modulator is given as a ratio between IMO and IAC with a
given VRMS when VEA
inversely proportional
is
to
saturated to HIGH. The gain is
VRMS2, as shown in Figure 29,
to implement line feed-forward. This automatically
adjusts the reference of current control error amplifier
according to the line voltage, such that the input power
of PFC converter is not changed with line voltage (as
shown in Figure 30).
Figure 26. Timing Diagram
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.0.0
IMO G IAC
IAC
K (VEA 0.6)
VRMS2 (VEAMAX 0.6)
Figure 28. Gain Modulator Block
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