ENH050Q1-450 Ver la hoja de datos (PDF) - White Electronic Designs Corporation
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ENH050Q1-450 Datasheet PDF : 21 Pages
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White Electronic Designs
Display Systems Division
ENH050Q1-320/450/600
Parameter
Horizontal
sync. output
pulse
[HSY]
Vertical
sync. output
pulse
[VSY]
Vertical
phase difference
Clock
output frequency
[CK]
INPUT/OUTPUT SIGNAL TIMING CHART (FIG. 6)
(CKC=HIGH, NTSC: fH=15.7kHz, fV=60Hz/PAL: fH=15.6kHZ, fV=50Hz)
pulse width
phase difference
rise time
fall time
pulse width
phase difference
rise time
fall time
odd field
even field
NTSC MODE
PAL MODE
NTSC MODE
PAL MODE
Symbol
tHS2
tPD
trHO
tfHO
tVS
tvHO
trVO
tfVO
tpV1
tpV2
fCLO
fCLO
fCLO
fCLO
Min.
Typ.
Max.
Unit
3.2
3.9
4.6
µs
0.4
1.1
1.8
µs
-
-
0.5
µs
-
-
0.5
µs
-
4H
-
µs
-
11.0
28.0
µs
-
-
2.0
µs
-
-
2.0
µs
-
1H
-
µs
-
0.5H
-
µs
-
fH
x
1201
2
-
MHz
-
fH
x
1209
2
-
MHz
-
fH
x
1201
6
-
MHz
-
fH
x
1209
6
-
MHz
(Supply voltage conditions: VSH = +8.0V, VSL = 5.0V)
Notes:
18. Adjusted by variable resister (H-POS) in a module.
19. Variable by variable resister (H-POS) in a module.
adjustment : tpd = 1, 1 ± 0.7 µs
20. Synchronized with HSY, based on falling timing of HSY.
21. VSY signal delays
22. Independent sampling mode.
23. Simultaneous sampling mode.
Reward
f=fH (18)
(19)
CL=10pF
1H=1/fH
(20)
CL=10pF
1H=1/fH
(21)
SAMC="Hi"
(22)
SAMC="Lo"
(23)
Display Time Range
NTSC (M) mode (NTP=High, CKC=High)
Displaying the following range within video signals.
• Horizontally: 12.2 ~ 63 µs
from the falling edge
of HSY. (SAM=High)
12.3 ~ 62.9 µs from the falling edge
of HSY. (SAM-Low)
• Vertically: 20 ~ 253 H
from the falling edge
of VSY.
PAL(B-G) Mode (NTP-Low, CKC=High)
Displaying the following range within video signals.
• Horizontally: 13.0 ~ 63.8 µs from the falling edge
of HSY. (SAM=High)
13.1 ~ 63.7 µs from the falling edge
of HSY. (SAM-Low)
• Vertically: 26 ~ 298 H
from the falling edge
of VSY.
However, the video signals of
(14n+12)H, (14n+20) H/Even field.
(14n+17)H, (14n+23) H/Odd field (n=1, 2..., 20)
are not displayed on the module.
External Clock Mode (NTP=High, CKC='Lo')
• Horizontally: 205 ~ 1164 ck from the falling edge
of HSY. (SAM=High)
84 ~ 403 ck
from the falling edge
of HSY. (SAM-Low)
(ck means input external clock.)
• Vertically: 20 ~ 253 H
from the falling edge
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Original specifications created by Sharp.
August 2003
Rev. 0
6
Display Systems Division • Hillsboro, OR • (503) 690-2460 • www.wedc.com
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