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EM78P569

8-BIT OTP MICRO-CONTROLLER

ELAN Microelectronics 

EM78P569

8-bit OTP Micro-controller

Bit 0 (/WUP80) : PORT80 wake-up control, 0/1 disable/enable P80 pin wake-up function

Bit 1 (/WUP81) : PORT81 wake-up control, 0/1 disable/enable P81 pin wake-up function

Bit 2 (/WUP82) : PORT82 wake-up control, 0/1 disable/enable P82 pin wake-up function

Bit 3 (/WUP83) : PORT83 wake-up control, 0/1 disable/enable P83 pin wake-up function

Bit 4 (PWM1) : PWM1 (Pulse Width Modulation channel 1) interrupt flag

Set when a selected period is reached, reset by software.

Bit 5 (ADI) : ADC interrupt flag after a sampling

Bit 6 (RBF) : SPI data transfer complete interrupt

If SPI's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set

this bit.

Bit 7 (PWM2) : PWM2 (Pulse Width Modulation channel 2) interrupt flag

Set when a selected period is reached, reset by software.

PAGE1 : (undefined) not allowed to use

PAGE2 (MSB 8-bit Multiplication result)

7

6

5

4

3

2

1

0

MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Bit 0 ~ Bit 7 (MR23 ~ MR16) : Multiplication result data

The multiplier can make a multiplication with X*Y. The multiplicator data buffer X is ACC(acculator) and

the multiplicand data buffer Y is RB PAGE2. The MSB 8-bit of maximum 24 bit multiplication result MR

will be stored in RE PAGE2.

RE PAGE2 = MR(16~23) = MSB 8-bit (X*Y)

PAGE3 : (undefined) not allowed to use

RF (Interrupt status)

(Interrupt status register)

7

6

5

4

3

2

1

0

INT3

-

INT2 INT1 INT0 CNT2 CNT1 TCIF

R/W-0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

"1" means interrupt request, "0" means non-interrupt

Bit 0(TCIF) : TCC timer overflow interrupt flag

Set when TCC timer overflows.

Bit 1(CNT1) : counter1 timer overflow interrupt flag

Set when counter1 timer overflows.

Bit 2(CNT2) : counter2 timer overflow interrupt flag

Set when counter2 timer overflows.

Bit 3(INT0) : external INT0 pin interrupt flag

If PORT70 has a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit.

Bit 4(INT1) : external INT1 pin interrupt flag

If PORT71 has a falling edge trigger signal, CPU will set this bit.

Bit 5(INT2) : external INT2 pin interrupt flag

If PORT72 has a falling edge trigger signal, CPU will set this bit.

Bit 6 : (undefined) not allowed to use

Bit 7(INT3) : external INT3 pin interrupt flag

If PORT73 has a falling edge trigger signal, CPU will set this bit.

<Note> IOCF is the interrupt mask register. User can read and clear.

__________________________________________________________________________________________________________________________________________________________________

* This specification is subject to be changed without notice.

26

8/19/2004 V4.4

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