EM83040BAQ Ver la hoja de datos (PDF) - ELAN Microelectronics

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EM83040BAQ

LCD CONTROLLER

ELAN Microelectronics 

EM83040B

LCD CONTROLLER

Preliminary

RAMD(3:0) are data or address of RAM. At the address mode, RAMADS is low and user should sent address

three times, from address (11:8) to address (3:0). Then it will go into data mode when RAMADS is high. In data

mode, user can sent one or more nibble data which address can be increased by internal counter.

Once the RAMEN pin is high, the RAM can not read and write.

(4)Read control

RAMEN

RAMADS

RAMD(3:0)

RAMW

RAMR

Ten

RAM enable

ADDRESS

A3 A2 A1

DATA

D1

Tdv

A3=address (11:8)

A2=address(7:4)

A1=address(3:0)

RAM disable

D2

Tdh

Tdd

D3

FIG. 4

As same as write mode, user has to sent address three times. And read data from RAM one by one which address

can be increased by internal counter. Note!! Be sure to make RAMR low pulse 2uS (Tdv +data) width and 2uS

(Tdd) high width at least.

(5) RAM mapping

RAM address is from 0 to address 2562

User fill “1” to LCD RAM, LCD driver will generate “light” waveform. Otherwise, it will generate a “dark”

waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address 19. And user

can refer to fig.5 and Table 1 to get the idea of LCD ram mapping. The other RAM can use as general RAM for

data storage if not mapping to LCD display. And the RAM of address 2560, 2561 and 2562 is control registers.

Table 1: LCD mapping RAM area

Common

Segment

32

48

32

80

48

32

48

80

64

16

64

80

80

0

80

80

Any

Any

Master/slave

Master

Slave

Master

Slave

Master

Slave

Master

Slave

Any

Display area

1,2,3

1,2,3,4

1,2,5,6

1,2,3,4,5,6,7

1,5,8

1,2,3,4,5,6,7,8,9

No mapping RAM

1,2,3,4,5,6,7,8,9,10

Area 11 is general RAM

* This specification are subject to be changed without notice.

9.14.2001 7

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