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EM78P157NAKM

8-Bit Microcontroller with OTP ROM

ELAN Microelectronics 

EM78P157N

8-Bit Microcontroller with OTP ROM

4.2.9 IOCF (Interrupt Mask Register)

Bit 7

-

Bit 6

-

Bit 5

-

Bit 4

-

Bit 3

-

Bit 2

EXIE

Bit 1

ICIE

Bit 0

TCIE

Individual interrupt is enabled by setting its associated control bit in the IOCF to "1."

Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.

Refer to Fig. 4-8 under Section 4.6.

IOCF register is both readable and writable.

Bit 0 (TCIE): TCIF interrupt enable bit

0: disable TCIF interrupt

1: enable TCIF interrupt

Bit 1 (ICIE): ICIF interrupt enable bit

0: disable ICIF interrupt

1: enable ICIF interrupt

Bit 2 (EXIE): EXIF interrupt enable bit

0: disable EXIF interrupt

1: enable EXIF interrupt

Bits 3~7: Not used.

4.3 TCC/WDT & Prescaler

An 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available

for either the TCC or WDT only at any given time, and the PAB bit of the CONT register

is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the

ratio. The prescaler is cleared each time the instruction is written to TCC under TCC

mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the

“WDTC” or “SLEP” instructions. Fig. 4-3 below, depicts the circuit diagram of

TCC/WDT.

„ R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or

external clock input (edge selectable from TCC pin). If TCC signal source is from

internal clock, TCC will increase by 1 at every instruction cycle (without prescaler).

Referring to Fig. 4-3 below, CLK=Fosc/2 or CLK=Fosc/4 application is determined

by the CODE Option bit CLK status. CLK=Fosc/2 is used when CLK bit is "0," and

CLK=Fosc/4 is used when CLK bit is "1." If TCC signal source comes from external

clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin.

12 •

Product Specification (V1.0) 09.22.2005

(This specification is subject to change without further notice)

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