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EM78P156ELKM Ver la hoja de datos (PDF) - ELAN Microelectronics

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EM78P156ELKM
EMC
ELAN Microelectronics EMC
EM78P156ELKM Datasheet PDF : 55 Pages
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EM78P156EL
OTP ROM
4. R3 (Status Register)
7
6
5
4
3
2
1
0
GP2
GP1
GP0
T
P
Z
DC
C
Bit 0 (C) Carry flag
Bit 1 (DC) Auxiliary carry flag
Bit 2 (Z) Zero flag.
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 3 (P) Power down bit.
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Bit 4 (T) Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT
time-out.
Bit5 ~7 (GP0 ~ 2) General-purpose read/write bits.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode.
• Bits 6~7 are not used (read only).
• The Bits 6~7 set to “1” at all time.
• Z flag of R3 will set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4 content will select
as R0.
• See the configuration of the data memory in Fig. 4.
6. R5 ~ R6 (Port 5 ~ Port 6)
• R5 and R6 are I/O registers.
• Only the lower 4 bits of R5 are available.
7. RF (Interrupt Status Register)
7
6
5
4
3
2
1
0
-
-
-
-
-
EXIF
ICIF
TCIF
“1” means interrupt request, and “0” means no interrupt occurs.
Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by
software.
Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
Bits 3 ~ 7 Not used.
• RF can be cleared by instruction but cannot be set.
This specification is subject to change without prior notice.
11
07.29.2004 (V1.3)

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