EM78910AAH Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM78910AAH Datasheet PDF : 30 Pages
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EM78910/910A
8-bit Micro-controller
sleep mode
/RINGTIME ='0'
or external keys
pressed
/RD and /CD ='1'
/RD and /CD ='1' and
nothing to do for 30
sec , /FSKPWR='0'
/FSKPWR='1'
wake up
mode
FSK decoder
begin its work
DATA transfer
to Micro
STATE Diagram between 8-bit
and FSK decoder
SLEEP MODE
Begin
set /FSKPWR='0'
No
/RINGTIME ='0'
or external keys
pressed
Yes
WAKE UP MODE
8-bit wake up and
set /FSKPWR='1'
accept data from
FSK decoder
Yes /RD and /CD ='1'
No
data end and 30
sec nothing to do.
Flow Diagram between 8-bit
and FSK decoder
Fig.6 The relation between Bit0 to Bit3.
* Bit 4 (/LOW-BAT) : (Read Only) Low battery detection output, 0/1 ! Battery voltage is low/Normal.
Low battery detection level is set by external resisters R1 and R2. The detection level VbL =
0.87V*(1+ R1/R2). If Vbattery is under VbL, then send a ‘0’ signal to /LOW_BAT bit; othwise a ‘1’
signal to this bit. Select pin P77/LBD as LBD by setting IOCE PAGE0 bit1 to ‘0’. LBD pin is used as
low battery detection input.
* Bit 5 (/LPD) : Power control of low battery detector, 0/1 ! Power on low battery detector/power off low
battery detector
The relation between /LPD, /POVD(see code option) and /LOW_BAT can see Fig7
VDD
Vbattery
R1
R2 LBD/P77
/POVD
s2
1 on
0 off
1 on
1 on
2.2V
Vref
LBD/P77
+-
/LPD
0 on
0 enable
To reset
SW
P77
+-
0.87V
/LOW_BAT
Fig.7 Universal low battery detector with /LPD, /POVD and /LOW_BAT
* Bit 6 (ENPLL) : PLL enable/disable control, 1/0 ! enable/disable
When ENPLL is enabled, CPU is in the normal mode
The relation between 32.768kHz and 3.579MHz can see Fig8.
S u b -c lo c k
3 2 .7 6 8 K H z
PLL
3 .5 7 9 M H z
R A b it6
1
sw itc h
0
T o sy ste m clo c k
Fig.8 The relation between 32.768kHz and 3.579MHz .
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
~ 8~
2001/01/12
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