EM78862B Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM78862B Datasheet PDF : 40 Pages
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EM78862B
8-Bit RISC Type Microprocessor
6 Functional Descriptions
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any
instruction using R0 as register actually accesses data pointed by the RAM Select Register
(R4).
6.1.2 R1 (TCC)
Increased by an external signal(16.384KHz or RC/2) , or by the instruction cycle clock.
Written and read by the program as any other register.
6.1.3 R2 (Program Counter)
The structure is depicted in Fig. 3 below.
Generates 16K × 13 on-chip ROM addresses to the relative programming instruction
codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC and PC+1, then push into the STACK
(14 bits).
"RET'' ("RETL k,” "RETI") instruction loads the program counter with the contents at the
top of stack.
"MOV R2, A" allows the loading of an address from the A register to the PC, and the 9th
and 10th bits are cleared to "0''.
"ADD R2, A" allows a relative address be added to the current PC, and contents of the
ninth and tenth bits are cleared to "0''.
"TBL" allows a relative address to be added into the current PC, and its 9th and 10th bits
content do not change. The most significant bit (A10~A13) will be loaded into the status
register (R5) with the contents of bits PS0~PS3 upon execution of a "JMP,'' "CALL,"
“MOV R2, A,'' "ADD R2, A,'' or ”TBL” instruction.
Fig. 3 Program Counter Organization
This specification is subject to change without further notice.
Mar.01.2005 (V1.1) 5 of 36
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