EM78R808A Ver la hoja de datos (PDF) - ELAN Microelectronics
Número de pieza
componentes Descripción
Fabricante
EM78R808A Datasheet PDF : 63 Pages
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EM78808
8-bit Micro-controller
TIP/RING
/CD
FSKDATA
/FSKPWR
FIRST RING
2 SECONDS 0.5 SEC
FSK signal
Tcdl
Tsup
Tdoc
DATA
SECOND RING
0.5 SEC 2 SECONDS
Tcdh
Fig.9 The relation between bit 1 ~ bit 3
The controller is a CMOS device designed to support the Caller Number Deliver feature which is offered
by the Regional Bell Operating Companies. The FSK block comprises one path: the signal path. The signal path
consist of an input differential buffer, a band pass filter, an FSK demodulator and a data valid with carrier detect
circuit.
In a typical application, user can use his own external ring detect output as a triggering input to IO port. User
can use this signal to wake up whole chip by external ring detect signal.
By setting “1” to bit 3 (FSKPWR) of register RA to activate the block of FSK decoder. If bit 3 (FSKPWR) of
register RA is set to “0”, the block of FSK decoder will be powered down.
The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this
signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends
it to a post filter. The output data is then made available at bit 2 (FSKDATA) of register RA. This data, as sent
by the central office, includes the header information (alternate "1" and "0") and 150 ms of marking which
precedes the date, time and calling number. If no data is present, the bit 2 (DATA) of register RA is held on “1”
state. This is accomplished by an carrier detect circuit which determines if the in-band energy is high enough. If
the incoming signal is valid, bit 1 (/CD) of register RA will be “0” otherwise it will be held on “1”. And thus the
demodulated data is transferred to bit 2 (DATA) of register RA. If it is not, then the FSK demodulator is
blocked.
Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list
below.
PLLEN
1
1
1
1
0
0
0
0
CLK1
CLK0
0
0
0
1
1
0
1
1
Don’t care don’t care
Don’t care don’t care
Don’t care don’t care
Don’t care don’t care
Sub clock
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
MAIN clock
CPU clock
895.658kHz 895.658kHz (Normal mode)
1.7913MHz 1.7913MHz (Normal mode)
10.7479MHz 10.7479MHz (Normal mode)
3.5826MHz 3.5826MHz (Normal mode)
Don’t care 32.768kHz (Green mode)
Don’t care 32.768kHz (Green mode)
Don’t care 32.768kHz (Green mode)
Don’t care 32.768kHz (Green mode)
______________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
8/1/2004 (V3.1)
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