EM73P461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
(10) Input/output
Mnemonic Object code (binary) Operation description
INA p
INM p
OUT #k,p
OUTA p
OUTM p
0110 1111 0100 pppp
0110 1111 1100 pppp
0100 1010 kkkk pppp
0110 1111 000p pppp
0110 1111 100p pppp
Acc←PORT[p]
RAM[HL]←PORT[p]
PORT[p]←k
PORT[p]←Acc
PORT[p]←RAM[HL]
(11) Flag manipulation
Mnemonic Object code (binary) Operation description
@ CGF
@ SGF
TFCFC
@ TGS
TTCFS
TZS
0101 0111
0101 0101
0101 0011
0101 0100
0101 0010
0101 1011
GF←0
GF←1
SF←CF', CF←0
SF←GF
SF←CF, CF←1
SF←ZF
(12) Interrupt control
Mnemonic Object code (binary) Operation description
CIL r
DICIL r
EICIL r
EXAE
RTI
0110 0011 11rr rrrr
0110 0011 10rr rrrr
0110 0011 01rr rrrr
0111 0101
0100 1101
IL←IL & r
EIF←0,IL←IL&r
EIF←1,IL←IL&r
MASK↔Acc
SP←SP+1,FLAG.PC
←STACK[SP],EIF ←1
(13) CPU control
Mnemonic Object code (binary) Operation description
NOP
0101 0110
no operation
@ : just for 4K ROM
Byte Cycle
Flag
C ZS
2
2
- Z Z'
2
2
- - Z'
2
2
- -1
2
2
- -1
2
2
- -1
Byte Cycle Flag
C ZS
1
1
- -1
1
1
- -1
1
1
0 -*
1
1
- -*
1
1
1 -*
1
1
- -*
Byte Cycle
2
2
2
2
2
2
1
1
1
2
Flag
C ZS
- -1
- -1
- -1
- -1
* **
Byte Cycle
1
1
Flag
C ZS
- --
* This specification are subject to be changed without notice.
12.27.2001 36