4342ILZ Ver la hoja de datos (PDF) - Intersil
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4342ILZ Datasheet PDF : 13 Pages
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EL4340, EL4342
AC Test Circuits
EL4340, EL4342
VIN
50Ω
OR
75Ω
CL
5PF
RL
500Ω
FIGURE 20A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
EL4340, EL4342
RS
VIN
50Ω
OR
75Ω
CL 475Ω
5PF
50Ω
OR
75Ω
TEST
EQUIPMENT
50Ω
OR
75Ω
FIGURE 20B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR
75Ω INPUT TERMINATED EQUIPMENT
EL4340, EL4342
RS
VIN
50Ω
CL 50Ω OR 75Ω
OR
5pF
75Ω
TEST
EQUIPMENT
50Ω
OR
75Ω
FIGURE 20C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE
APPLICATION. BANDWIDTH AND LINEARITY
FOR RL LESS THAN 500Ω WILL BE DEGRADED.
FIGURE 20. TEST CIRCUITS
Figure 20A illustrates the optimum output load for testing AC
performance. Figure 20B illustrates the optimun output load
when connecting to 50Ω input terminated equipment.
Application Information
General
The EL4340, EL4342 triple 2:1 and 4:1 MUX amps are ideal
as the matrix element of high performance switchers and
routers. Key features include buffered high impedance
analog inputs and excellent AC performance at output loads
down to 150Ω for video cable-driving. The unity-gain current
feedback output amplifiers are stable operating into
capacitive loads and bandwidth is optimized with a load of
5pF in parallel with a 500Ω. Total output capacitance can be
split between the PCB capacitance and an external load
capacitor.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins
and NIC pins must connect to the GND plane.
Control Signals
S0, S1, ENABLE, LE, HIZ - These are binary coded,
TTL/CMOS compatible control inputs. The S0, S1 pins select
the inputs. All three amplifiers are switched simultaneously
from their respective inputs. The ENABLE, LE, HIZ pins are
used to disable the part to save power, latch in the last logic
state and three-state the output amplifiers, respectively. For
control signal rise and fall times less than 10ns the use of
termination resistors close to the part will minimize transients
coupled to the output.
Power-up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can
flow for power supply rates-of-rise in excess of 1V/µs, such
as during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 21) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through
the ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
V+ SUPPLY
LOGIC
POWER
GND
SIGNAL
DE-COUPLING
CAPS
V- SUPPLY
SCHOTTKY
PROTECTION
V+
S0
GND V- V+
IN0
IN1
V+
V-
V-
V+
LOGIC
CONTROL
V-
V+
OUT
V-
FIGURE 21. SCHOTTKY PROTECTION CIRCUIT
EXTERNAL
CIRCUITS
9
FN7421.3
October 18, 2010
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