EL4583A Ver la hoja de datos (PDF) - Intersil

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EL4583A

Sync Separator, 50% Slice, S-H, Filter, HOUT

Intersil 

EL4583A

FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL

Description of Operation

A simplified block schematic is shown in Figure 1. The

following description is intended to provide the user with

sufficient information to understand the effects of the

external components and signal conditions on the outputs of

the integrated circuit.

The video signal is AC coupled to pin 4 via the capacitor C1,

nominally 0.1µF. The clamp circuit A1 will prevent the input

signal on pin 4 going more negative than 1.5V, the value of

reference voltage VR1. Thus the sync tip, the most negative

part of the video waveform, will be clamped at 1.5V. The

current source I1, nominally 6µA, charges the coupling

capacitor during the remaining portion of the H line,

approximately 58µs for a 15.75kHz timebase. From I • t = C •

V, the video time-constant can be calculated. It is important

to note that the charge taken from the capacitor during video

must be replaced during the sync tip time, which is much

shorter, (ratio of x 12.5). The corresponding current to

restore the charge during sync will therefore be an order of

magnitude higher, and any resistance in series with CI will

cause sync tip crushing. For this reason, the internal series

resistance has been minimized and external high resistance

values in series with the input coupling capacitor should be

avoided. The user can exercise some control over the value

of the input time constant by introducing an external pull-up

resistance from pin 4 to the 5V supply. The maximum

voltage across the resistance will be VDD less 1.5V, for black

level. For a net discharge current greater than zero, the

resistance should be greater than 450k. This will have the

effect of increasing the time constant and reducing the

degree of picture tilt. The current source I1 directly tracks

reference current ITR and thus increases with scan rate

adjustment, as explained later.

The signal is processed through an active 3 pole filter (F1)

designed for minimum ripple with constant phase delay. The

filter attenuates the color burst by 12dB and eliminates fast

transient spikes without sync crushing. An external filter is

not necessary. The filter also amplifies the video signal by

6dB to improve the detection accuracy. The filter cut-off

frequency is controlled by an external resistor from pin 1 to

ground.

Internal reference voltages (block VREF) with high immunity

to supply voltage variation are derived on the chip.

Reference VR4 with op-amp A2 forces pin 12 to a reference

voltage of 1.7V nominal. Consequently, it can be seen that

the external resistance RSET will determine the value of the

reference current ITR. The internal resistance R3 is only

about 6kΩ, much less than RSET. All the internal timing

8

FN7503.2

November 12, 2010

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