RF2175 Ver la hoja de datos (PDF) - RF Micro Devices
Número de pieza
componentes Descripción
Fabricante
RF2175 Datasheet PDF : 6 Pages
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RF2175
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pkg
Base
Function
VCC
L TUNE
NC
Q1C
GND1
RF IN
NC
VREG
NC
NC
NC
RF OUT
RF OUT
RF OUT
NC
VBIAS
GND
Description
Interface Schematic
Power supply for input bias circuitry. A 1nF high frequency bypass
capacitor is recommended.
Interstage Tuning. A shunt inductor to GND is required to optimize the
match.
No connection.
Power supply for stage 1. VCC should be fed through a 25nH or greater
inductor with a decoupling capacitor on the VCC side.
Ground for stage 1. For best performance, keep traces physically short
and connect immediately to ground plane. This ground should be iso-
lated from the backside ground contact.
RF input. An external DC blocking capacitor is required if this port is
connected to a DC path to ground or a DC voltage.
No connection.
Power Down control. When this pin is “low”, all circuits are shut off.
When this pin is 2.8V, all circuits are operating normally. VPD requires a
regulated 2.8V for the amplifier to operate properly over all specified
temperature and voltage ranges. A dropping resistor from a higher reg-
ulated voltage may be used to provide the required 2.8V. A 100pF high
frequency bypass capacitor is recommended.
No connection.
No connection.
No connection.
RF output and power supply for the output stage. The bias for the out-
put stage is provided through this pin and pin 13. An external matching
network is required to provide the optimum load impedance; see the
application schematics for details.
Same as pin 12.
Harmonic trap. This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating fre-
quency. An inductor or transmission line resonating with a shunt
capacitor at 2f0 is connected to this pin.
No connection.
The bias pin allows higher efficiency in low power power modes. When
operating at full output, VBIAS should be 2.8V.
Ground connection. The backside of the package should be soldered to
a top side ground pad, which is connected to the ground plane with
multiple vias. The pad should have a short thermal path to the ground
plane.
Rev A8 030313
2-289
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