EDS2516APTA Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EDS2516APTA

256M bits SDRAM

Elpida Memory, Inc 

EDS2516APTA

AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)

-60

-7A

-75

Parameter

Symbol min.

max.

min.

max.

min.

max.

Unit

Notes

System clock cycle time tCK

6

—

7.5

—

7.5

—

ns

1

CLK high pulse width

tCH

2.5

—

2.5

—

2.5

—

ns

1

CLK low pulse width

tCL

Access time from CLK

tAC

Data-out hold time

tOH

CLK to Data-out low

impedance

tLZ

CLK to Data-out high

Eimpedance

tHZ

Input setup time

tSI

Input hold time

tHI

Ref/Active to Ref/Active

Ocommand period

tRC

Active to Precharge

command period

tRAS

Active command to column

L command (same bank)

tRCD

2.5

—

2.5

1

—

1.5

1

60

42

18

—

2.5

5.0

—

—

3.0

—

1

5.0

—

—

1.5

—

0.8

—

60

120000 45

—

15

—

2.5

5.4

—

—

3.0

—

1

5.4

—

—

1.5

—

0.8

—

67.5

120000 45

—

20

—

ns

5.4

ns

—

ns

—

ns

5.4

ns

—

ns

—

ns

—

ns

120000 ns

—

ns

1

1, 2

1, 2

1, 2, 3

1, 4

1

1

1

1

1

Precharge to active

command period

tRP

18

—

15

—

20

—

ns

1

Write recovery or data-in to

precharge lead time

tDPL

12

—

15

—

15

—

ns

1

Last data into active

latency

tDAL

2CLK +

18ns

—

2CLK +

15ns

—

2CLK +

20ns

—

Active (a) to Active (b)

P command period

tRRD

12

—

15

—

15

—

ns

1

Transition time (rise and

fall)

tT

0.5

5

0.5

5

0.5

5

ns

Refresh period

(8192 refresh cycles)

tREF

—

64

—

64

—

64

ms

r Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

2. Access time is measured at 1.4V. Load condition is CL = 50pF.(in case of -60, CL = 30pF)

o 3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

duct 4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

Data Sheet E0359E20 (Ver. 2.0)

7

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