EDS2516APTA Ver la hoja de datos (PDF) - Elpida Memory, Inc

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Fabricante

EDS2516APTA

256M bits SDRAM

Elpida Memory, Inc 

EDS2516APTA

DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)

Parameter

/CAS latency

Symbol

Grade max.

Unit

Test condition

Notes

Operating current

ICC1

-60, -7A 135

-75

115

mA

Burst length = 1

tRC = tRC (min.)

1, 2, 3

Standby current in power down ICC2P

Standby current in power down

(input signal stable)

ICC2PS

Standby current in non power down ICC2N

Standby current in non

(input signal stable)

power

down

ICC2NS

EActive standby current in power

down

ICC3P

Active standby current in power

down (input signal stable)

ICC3PS

Active standby current in non

Opower down

ICC3N

Active standby current in non

power down (input signal stable)

ICC3NS

L Burst operating current

ICC4

3

2

20

9

4

3

30

15

-60

180

-7A, -75 145

mA

CKE = VIL,

tCK = tCK (min.)

6

mA

CKE = VIL, tCK = ∞ 7

mA

CKE, /CS = VIH,

tCK = tCK (min.)

4

mA

CKE = VIH, tCK = ∞,

/CS = VIH

8

mA

CKE = VIL,

tCK = tCK (min.)

1, 2, 6

mA

CKE = VIL, tCK = ∞ 2, 7

mA

CKE, /CS = VIH,

tCK = tCK (min.)

1, 2, 4

mA

CKE = VIH, tCK = ∞,

/CS = VIH

2, 8

mA

tCK = tCK (min.),

BL = 4

1, 2, 5

Refresh current

ICC5

-60, -7A 250

-75

220

mA

tRC = tRC (min.)

3

Self refresh current

ICC6

3

mA

VIH ≥ VDD – 0.2V

VIL ≤ 0.2V

Self refresh current

(L-version)

ICC6

-XXL

1

mA

VIH ≥ VDD – 0.2V

VIL ≤ 0.2V

P Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output

open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

r 5. Input signals are changed once per four clocks.

6. After power down mode, CLK operating current.

o 7. After power down mode, no CLK operating current.

duct 8. Input signals are VIH or VIL fixed.

Data Sheet E0359E20 (Ver. 2.0)

5

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