EDI8L32512C Ver la hoja de datos (PDF) - White Electronic Designs Corporation
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EDI8L32512C Datasheet PDF : 8 Pages
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EDI8L32512C
512K x 32 CMOS High Speed Static RAM
FEATURES
DESCRIPTION
n DSP Memory Solution
Motorola DSP96002
Analog SHARC DSP
Texas Instruments TMS320C3x, TMS320C4x
n Random Access Memory Array
Fast Access Times: 12*, 15, 17, and 20ns
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
n Surface Mount Package
68 Lead PLCC, No. 99 JEDEC M0-47AE
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum
Noise Immunity
n Single +5V (±5%) Supply Operation
* Advance Information.
The EDI8L32512C is a high speed, 5V, 16 megabit
SRAM. The device is available with access times of
12, 15, 17 and 20ns allowing the creation of a no wait
state DSP memory solution. The high speed, 5V
supply voltage and control lines make the device ideal
for creating floating point DSP memory solutions.
The device can be configured as a 512K x 32 and used
to create a single chip external data memory solution for
TI's TMS320C30/C31 (Figure 8), TMS320C32 (Figure 9)
or TMS320C4x (Figure 10), Motorola's DSP96002 and
Analog's SHARC DSP (Figure 11). Alternatively, the
device's chip enables can be used to configure it as a 1M
x 16. A 1M x 48 program memory array for Analog's
SHARC DSP is created using three devices (Figure 12).
If this memory is too deep, two 512K x 24s (EDI8L24512C)
can be used to create a 512K x 48 array or two 128K x 24s
(EDI8L24128C) can be used to create a 128K x 48 array.
The device provides a 56% space savings when
compared to four 512K x 8, 36 pin SOJs. In addition
the EDI8L32512C has only a 10pF load on the data
lines vs. 32pF for four plastic SOJs.
The device provides a memory upgrade of the
EDI8L32256C (256K x 32) or the EDI8L32128C (128K x
32). For additional upgrade information see Figure 13.
Note: Solder Reflow Temperature should not exceed 230°C for 10 seconds.
FIG. 1 PIN CONFIGURATIONS AND BLOCK DIAGRAM
PIN NAMES
DQ17 10
DQ18 11
DQ19 12
VSS 13
DQ20 14
DQ21 15
DQ22 16
DQ23 17
VCC 18
DQ24 19
DQ25 20
DQ26 21
DQ27 22
VSS 23
DQ28 24
DQ29 25
DQ30 26
60 DQ14
59 DQ13
58 DQ12
57 VSS
56 DQ11
55 DQ10
54 DQ9
53 DQ8
52 VCC
51 DQ7
50 DQ6
49 DQ5
48 DQ4
47 VSS
46 DQ3
45 DQ2
44 DQ1
Note: For memory upgrade information, refer to Page 8, Figure 13
"EDI MCM-L Upgrade Path."
A0-18
E0-3
W
G
DQ0-31
VCC
VSS
NC
Address Inputs
Chip Enables (One per Byte)
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (+5V ±5%)
Ground
No Connection
A0-18 19
G
W
E0
E1
E2
E3
512K x 32
Memory
Array
BYTE CONTROL
TABLE
Chip
Enable
E0
E1
E2
E3
Byte
Control
DQ0-7
DQ8-15
DQ16-23
DQ24-31
DQ0-7
DQ8-15
DQ16-23
DQ24-31
August 2000 Rev. 7
ECO #13097
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
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