EDI2DL32256V Ver la hoja de datos (PDF) - White Electronic Designs Corporation

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EDI2DL32256V

256Kx32 Synchronous Pipline Burst SRAM 3.3V

White Electronic Designs Corporation 

EDI2DL32256V

FIG. 5

INTERFACING THE TEXAS INSTRUMENTS TMS320C6201

WITH THE EDI2DL32256V (256Kx32 SSRAM)

EA0-22

CE2\

CE1\

CE0\

BE3\

Texas Instruments BE2\

TMS320C6201 BE1\

BE0\

SSOE\

SSADS\

SSADV\

SSWE\

CLKOUT1

CLKOUT2

ED0-31

(NOTE 1)

CE\

A0-17

MODE

(NOTE 4)

NC, Vss, Vcc

ZZ (NOTE 2)

BE3\

BE2\

BE1\ EDI2DL32256V

BE0\

OE\

ADSC\

ADV\

GW\ (NOTE 3)

CLK

DQ0-31

NOTES:

1. Either CE0 or CE2 can be used to enable the device.

2. When the ZZ pin is asserted HIGH, the device will be in CMOS standby mode regardless of the state of any other pins. While in standby mode the device will

take one complete Clock cycle to become active again after a LOW is asserted on the ZZ pin. One possible option for the designer concerned about power is

to tie the ZZ signal to the chip enable they are using for the device. Any time the chip is disabled (by driving the chip enable pin HIGH) the device will go into

standby mode. Standby mode can also be achieved by tying the ZZ pin LOW or allowing it to float and meeting all the signal conditions specified in the data

sheet.

3. Use CLKOUT1 for running the memory at the same clock speed as the C6x. Use CLKOUT2 for running the SBSRAM at one half the clock rate of the C6x.

4. The MODE pin can be tied to Vss (Linear Burst), tied to Vcc (Interleaved Burst) or allowed to float (Interleaved Burst).

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

8

November 2000, Rev. 1

ECO #13417

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