EDE1108ABSE-8E-E Ver la hoja de datos (PDF) - Elpida Memory, Inc
Número de pieza
componentes Descripción
Fabricante
EDE1108ABSE-8E-E Datasheet PDF : 27 Pages
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EBE21EE8ABFA
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
2
Module data width
0 1 0 0 1 0 0 0 48H
72
Module data width continuation
Voltage interface level of this
assembly
DDR SDRAM cycle time, CL = 5
-8E
-6E
-5C
-4A
SDRAM access from clock (tAC)
-8E
-6E
-5C
-4A
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 1 0 1 05H
0 0 1 0 0 1 0 1 25H
0 0 1 1 0 0 0 0 30H
0 0 1 1 1 1 0 1 3DH
0 1 0 1 0 0 0 0 50H
0 1 0 0 0 0 0 0 40H
0 1 0 0 0 1 0 1 45H
0 1 0 1 0 0 0 0 50H
0 1 1 0 0 0 0 0 60H
0
SSTL 1.8V
2.5ns*1
3.0ns*1
3.75ns*1
5.0ns*1
0.4ns*1
0.45ns*1
0.5ns*1
0.6ns*1
DIMM configuration type
0 0 0 0 0 0 1 0 02H
ECC
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1 01H
0
4,8
8
3, 4, 5
4.00mm max.
DIMM type information
0 0 0 0 0 0 1 0 02H
Unbuffered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4
-8E, -6E, -5C
0
0
1
1
1
1
0
1
3DH
-4A
0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC)
from clock at CL = 4
0 1 0 1 0 0 0 0 50H
-8E, -6E, -5C
-4A
0 1 1 0 0 0 0 0 60H
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
Normal
Weak Driver
50Ω ODT Support
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
Maximum data access time (tAC)
from clock at CL = 3
01
10
00
00
60H
0.6ns*1
Preliminary Data Sheet E0907E10 (Ver. 1.0)
5
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