EBD11UD8ABFA Ver la hoja de datos (PDF) - Elpida Memory, Inc
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EBD11UD8ABFA Datasheet PDF : 18 Pages
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EBD11UD8ABFA
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 to 26
27
28
29
30
31
32
33
34
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 0 1 1 1 07H
Number of row address
0 0 0 0 1 1 0 1 0DH
Number of column address
0 0 0 0 1 0 1 1 0BH
Number of DIMM banks
0 0 0 0 0 0 1 0 02H
Module data width
0 1 0 0 0 0 0 0 40H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
DDR SDRAM cycle time, CL = 2.5 0 1 1 1 0 1 0 1 75H
SDRAM access from clock (tAC)
0 1 1 1 0 1 0 1 75H
DIMM configuration type
0 0 0 0 0 0 0 0 00H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01H
column access
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 0 1 01H
0 0 0 0 0 0 1 0 02H
SDRAM module attributes
0 0 1 0 0 0 0 0 20H
SDRAM device attributes: General 0 1 0 0 0 0 0 0 40H
Minimum clock cycle time at CL = 2 0 1 1 1 0 1 0 1 75H
Maximum data access time (tAC) from
clock at CL = 2
0
1
1
1
0
1
0
1
75H
0 0 0 0 0 0 0 0 00H
Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50H
Minimum row active to row active
delay (tRRD)
0 0 1 1 1 1 0 0 3CH
Minimum /RAS to /CAS delay (tRCD) 0 1 0 1 0 0 0 0 50H
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
Module bank density
1 0 0 0 0 0 0 0 80H
Address and command setup time
before clock (tIS)
1 0 0 1 0 0 0 0 90H
Address and command hold time after
clock (tIH)
1
0
0
1
0
0
0
0
90H
Data input setup time before clock
(tDS)
0 1 0 1 0 0 0 0 50H
Comments
128 bytes
256 bytes
DDR SDRAM
13
11
2
64
0
SSTL2
7.5ns
0.75ns
None.
7.6µs
×8
None.
1 CLK
2,4,8
4
2, 2.5
0
1
Differential
Clock
VDD ± 0.2V
7.5ns
0.75ns
20ns
15ns
20ns
45ns
512M bytes
0.9ns
0.9ns
0.5ns
Preliminary Data Sheet E0281E10 (Ver. 1.0)
5
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