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E28F004BL-T150

4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY

Intel 

28F400BL-T B 28F004BL-T B

Program Setup (40H or 10H)

This command simply sets the CUI into a state such

that the next write will load the address and data

registers Either 40H or 10H can be used for Pro-

gram Setup Both commands are included to ac-

commodate efforts to achieve an industry standard

command code set

Program

The second write after the program setup command

will latch addresses and data Also the CUI initiates

the WSM to begin execution of the program algo-

rithm While the WSM finishes the algorithm the de-

vice will output Status Register contents Note that

the WSM cannot be suspended during program-

ming

Erase Setup (20H)

Prepares the CUI for the Erase Confirm command

No other action is taken If the next command is not

an Erase Confirm command then the CUI will set

both the Program Status and Erase Status bits of the

Status Register to a ‘‘1’’ place the device into the

Read Status Register state and wait for another

command

Erase Confirm (D0H)

If the previous command was an Erase Setup com-

mand then the CUI will enable the WSM to erase at

the same time closing the address and data latches

and respond only to the Read Status Register and

Erase Suspend commands While the WSM is exe-

cuting the device will output Status Register data

when OE is toggled low Status Register data can

only be updated by toggling either OE or CE low

Erase Suspend (B0H)

This command only has meaning while the WSM is

executing an Erase operation and therefore will only

be responded to during an erase operation After

this command has been executed the CUI will initi-

ate the WSM to suspend Erase operations and then

return to responding to only Read Status Register or

to the Erase Resume commands Once the WSM

has reached the Suspend state it will set an output

into the CUI which allows the CUI to respond to the

Read Array Read Status Register and Erase Re-

sume commands In this mode the CUI will not re-

spond to any other commands The WSM will also

set the WSM Status bit to a ‘‘1’’ The WSM will con-

tinue to run idling in the SUSPEND state regardless

of the state of alI input control pins with the exclu-

sion of RP RP low will immediately shut down

the WSM and the remainder of the chip

Erase Resume (D0H)

This command will cause the CUI to clear the Sus-

pend state and set the WSM Status bit to a ‘‘0’’ but

only if an Erase Suspend command was previously

issued Erase Resume will not have any effect in all

other conditions

4 4 3 STATUS REGISTER

The 4 Mbit flash family contains a status register

which may be read to determine when a program or

erase operation is complete and whether that oper-

ation completed successfully The status register

may be read at any time by writing the Read Status

command to the CUI After writing this command all

subsequent Read operations output data from the

status register until another command is written to

the CUI A Read Array command must be written to

the CUl to return to the Read Array mode

The status register bits are output on DQ 0 7

whether the device is in the byte-wide (x8) or word-

wide (x16) mode for the 28F400BL In the word-wide

mode the upper byte DQ 8 15 is set to 00H during

a Read Status command In the byte-wide mode

DO 8 14 is tri-stated and DQ15 Ab1 retains the low

order address function

It should be noted that the contents of the status

register are latched on the falling edge of OE or

CE whichever occurs last in the read cycle This

prevents possible bus errors which might occur if the

contents of the status register change while reading

the status register CE or OE must be toggled

with each subsequent status read or the completion

of a program or erase operation will not be evident

The Status Register is the interface between the mi-

croprocessor and the Write State Machine (WSM)

When the WSM is active this register will indicate

the status of the WSM and will also hold the bits

indicating whether or not the WSM was successful in

performing the desired operation The WSM sets

status bits ‘‘Three’’ through ‘‘Seven’’ and clears bits

‘‘Six’’ and ‘‘Seven’’ but cannot clear status bits

‘‘Three’’ through ‘‘Five’’ These bits can only be

cleared by the controlling CPU through the use of

the Clear Status Register command

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